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The low thermal conductivity of β-Ga2O3 is a significant concern for maximizing the potential of this ultra-wide bandgap semiconductor as a power switching device technology. Here, we report on the use of nanocrystalline diamond (NCD) deposited via microwave plasma enhanced chemical vapor deposition (MP-CVD) as a top-side, device-level thermal management solution on a lateral β-Ga2O3 transistor. NCD was grown via MP-CVD on β-(AlxGa1−x)2O3/β-Ga2O3 heterostructures prior to the gate formation of the field-effect transistor. A reduced growth temperature of 400 °C and a SiNx barrier layer were used to protect the oxide semiconductors from etching in the MP-CVD H2 plasma environment. Raman spectroscopy showed a highly sp3-bonded NCD film was obtained at 400 °C, with grain size of about 50–100 nm imaged via atomic force microscopy. The incorporation of the NCD heat-spreading layer resulted in a β-(AlxGa1−x)2O3/β-Ga2O3 heterostructure field-effect transistor showing a decrease in the total thermal resistance at the gate by 42%. The fabrication process, including the NCD etch in the gate region, will need to be improved to minimize the impact of these processes on important device characteristics (i.e., drain current, threshold voltage, and leakage current). [ABSTRACT FROM AUTHOR]

This work demonstrates direct, rapid 2D thermal mapping measurement capabilities of the ultrawide bandgap semiconductor channel of lateral β-(AlxGa1−x)2O3/Ga2O3 transistors without sample contamination, long acquisition times, or sophisticated thermometry such as developing deep-ultra-violet compatible thermoreflectance systems. The temperature rise in the channel of a β-(Al0.21Ga0.79)2O3/Ga2O3 heterostructure field-effect transistor (HFET) was mapped using thermoreflectance imaging at 470 nm. First, the thermoreflectance response of the HFET channel was measured using a monochromator, revealing a maximum of the reflectance change around 470–480 nm. Thermoreflectance calibrations were then performed at 470 nm (peak of the reflectance change) and yielded an average thermoreflectance coefficient of 1.06 ± 0.07 × 10−4 K−1. Subsequent measurements of the device (power densities of 0.15–1.47 W/mm and gate-source voltage of 0 V) enabled extraction of a device-level thermal resistance of 51.1 mm·K/W in the channel at the drain-side of the gate. High-resolution, in situ scanning thermal microscopy measurements of the channel temperature rise show good agreement with and further support the thermoreflectance measurements. Finally, the thermal profile across the entire device length (metal electrodes and semiconductor channel) and width was simultaneously measured using thermoreflectance imaging at 470 nm, and the peak temperature rise was measured in the channel at the drain-side of the gate electrode. [ABSTRACT FROM AUTHOR]