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In recent years, the energy consumption of IoT edge nodes has significantly increased due to the communication process. This necessitates the need to offload more computation to the edge nodes to minimize data transmission over the network. To achieve this, higher-performance CPUs and memory are required on the edge nodes. In this context, we propose an energy-efficient memory architecture specifically designed for edge nodes. STT-MRAM is a promising memory technology that offers potential replacements for SRAM and Flash in IoT devices. STT-MRAM exhibits notable advantages over traditional memory technologies, such as non-volatility for data retention without continuous power supply and energy efficiency, resulting in extended battery life for portable devices and IoT applications. Its potential for higher memory density and scalability through standard fabrication processes further enhances its appeal for next-generation memory solutions. However, the high write energy consumption is its main disadvantage. Previous works have explored non-volatility relaxation in CPU cache but there is a need to extend this approach to main memory in IoT devices. In this paper, we propose a multi-retention STT-MRAM architecture for IoT main memory. Additionally, we propose a memory mapping scheme for the suggested memory architecture and examine the impact of more relaxed retention levels on energy consumption. To the best of our knowledge, this is the first study to thoroughly investigate the optimal thermal stability factor value for STT-MRAM in IoT applications while also considering optimal memory mapping. The proposed architecture reduces energy consumption by an average of 70% and up to 83% compared to the currently used non-volatile STT-MRAM architecture. Furthermore, we propose two memory mappings that are easy to use and achieve an average energy savings that is just 5% away from the ideal mapping.

In advanced integrated circuit manufacturing, the quality of chemical mechanical polishing (CMP) is a key factor affecting chip performance and yield. Designers need to use CMP simulation tools to locate and analyze the defects in the layout after the CMP process. However, the advancement of process nodes and the increase in data volume presents a great challenge to the speed of graphical display of CMP simulation data. To solve this issue, we propose a solution that uses multi-threading technology to optimize both data reading and drawing. In the process of data reading, we employ OpenMP and memory mapping (Mmap) technology to achieve parallel reading of file segmentation and propose a fast-string conversion algorithm based on the properties of simulation data. In the process of data drawing, we propose an adaptive downsampling method for data graphical display that combines multi-threading and double buffering technology to enable the parallel drawing of layouts. The effectiveness of this method is verified by testing CMP simulation data of various scales. Compared to traditional methods, this approach improves reading efficiency by over 8 times and drawing efficiency by more than 10 times. Furthermore, it enhances the smoothness of interaction with the CMP simulation tool. [ABSTRACT FROM AUTHOR]