Search

Applications in industrial production have indicated that the challenges of sparse fault samples and singular monitoring data will diminish the performance of deep learning-based diagnostic models to varying degrees. To alleviate the above issues, a multi-source information fusion meta-learning network with convolutional block attention module (CBAM) is proposed in this study for bearing fault diagnosis under limited dataset. This method can fully extract and exploit the complementary and enriched fault-related features in the multi-source monitoring data through the designed multi-branch fusion structure and incorporate metric-based meta-learning to enhance the fault diagnosis performance of the model under limited data samples. Furthermore, the introduction of CBAM can further assist the model to trade-off and focus on more discriminative information in both spatial and channel dimensions. Extensive experiments conducted on two bearing datasets that cover multi-source monitoring data fully demonstrate the validity and superiority of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246. [ABSTRACT FROM AUTHOR]