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In this article, we comprehensively investigate the potential of the digital polar radio transmitter architecture for multi-user massive multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) downlink system. In terms of throughput performance, we derive a lower bound for the average sum-rate achievable with Gaussian signaling inputs and zero-forcing (ZF) precoding based on Bussgang decomposition. By diagonal approximation, we derive an approximate, yet accurate, model for the distortion caused by uniform polar quantization, which can be used to evaluate the corresponding sum-rate in closed form. To assess the power efficiency, we provide power consumption models with realistic parameters and values for the quantized polar and Cartesian transmitters, based on state-of-the-art integrated circuit (IC) designs and measurements. Extensive numerical results demonstrate that the proposed quantized polar transmitter can enable excellent performance in terms of average sum-rate, symbol error rate (SER), and out-of-band (OOB) emission level, compared to the Cartesian architecture. Furthermore, the power consumption comparisons show that the digital polar transmitter can save more than 36% in the energy consumption under 64-antenna setting in typical 5G enhanced mobile broadband use cases, thus making it highly appealing for future power-efficient massive MIMO transmitter implementations.

The digital front-end of the communication transceivers envisioned for fifth-generation (5G) and beyond requires highly configurable high-performance digital signal processing (DSP) hardware operating at very high sampling rates to accommodate increasing signal bandwidths and support a range of modulation schemes and transmitter architectures. In this article, we present an efficient implementation of a highly configurable DSP hardware generator that can generate high-performance DSP hardware for multiple transmitter architectures including Cartesian, polar, outphasing, and multilevel outphasing modulators. The generated hardware unit, which consists of multistage multirate filters and other required DSP operations, runs at sample rates up to 4 GHz. The hardware supports an adjacent channel leakage ratio (ACLR) down to −48 dB and an error vector magnitude (EVM) of 0.78% with a 7-bit phase signal at a sampling rate of 4 GHz for multilevel outphasing modulation. Digital synthesis of the circuit in a 5-nm complimentary metal-oxide semiconductor (CMOS) process yields a core area consumption of 0.01 mm2 and an estimated power consumption of 37.2 mW for a 200-MHz bandwidth 5G new radio (NR) baseband (BB) signal.