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Neural recording systems play a crucial role in comprehending the intricacies of the brain and advancing treatments for neurological disorders. Within these systems, the analog-to-digital converter (ADC) serves as a fundamental component, converting the electrical signals from the brain into digital data that can be further processed and analyzed by computing units. This research introduces a novel nonlinear ADC designed specifically for spike sorting in biomedical applications. Employing MOSFET varactors and voltage-controlled oscillators (VCOs), this ADC exploits the nonlinear capacitance properties of MOSFET varactors, achieving a parabolic quantization function that digitizes the noise with low resolution and the spikes with high resolution, effectively suppressing the background noise present in biomedical signals. This research aims to develop a reconfigurable, nonlinear voltage-controlled oscillator (VCO)-based ADC, specifically designed for implantable neural recording systems used in neuroprosthetics and brain–machine interfaces. The proposed design enhances the signal-to-noise ratio and reduces power consumption, making it more efficient for real-time neural data processing. By improving the performance and energy efficiency of these devices, the research contributes to the development of more reliable medical technologies for monitoring and treating neurological disorders. The quantization step of the ADC spans from 44.8 mV in the low-amplitude range to 1.4 mV in the high-amplitude range. The circuit was designed and simulated utilizing a 180 nm CMOS process; however, no physical prototype has been fabricated at this stage. Post-layout simulations confirm the expected performance. Occupying a silicon area is 0.09 mm2. Operating at a sampling frequency of 16 kS/s and a supply voltage of 1 volt, this ADC consumes 62.4 µW. [ABSTRACT FROM AUTHOR]

A multiplex, delay‐and‐sum (MDAS) architecture is proposed to implement a fixed‐focus receive beamformer such as the first stage of the synthetic aperture sequential beamforming (P‐SASB) and synthetic transmit beams combined with the P‐SASB (STB‐P‐SASB) beamforming methods. The output image of this architecture has a resolution and contrast‐to‐noise ratio (CNR) almost similar to that of the delay‐and‐sum (DAS) architecture. In the analog part of this architecture, there is no need to use any analog memory and in the digital part, the need to use high‐speed memories and interpolation filter is eliminated. In this architecture for each input channel, the power consumption in the mixed‐signal part is increased by approximately 1.14 mW in comparison to that of the DAS architecture. On the other hand, due to the elimination of the power consumption related to the interpolation filter in the digital part, the total power consumption of the MDAS architecture increases by a maximum of 9.2% compared to the DAS architecture. Also, the silicon area required to implement the mixed‐signal part of the MDAS architecture when implementing the first stage of P‐SASB and STB‐P‐SASB beamforming methods is reduced by about 3 times and increased by a maximum of 25%, respectively, compared to that of the DAS architecture. [ABSTRACT FROM AUTHOR]

Summary: In this article, a compact integrated high‐voltage (HV) pulser is presented, which can serve as an actuator in area‐limited medical ultrasound imaging applications. The proposed HV pulser is capable of producing bipolar return‐to‐zero (RTZ) HV pulses with a maximum peak‐to‐peak amplitude of 60 V. A novel RTZ stage including a new transistor gate–source protection scheme is used in this work, resulting in a reduced die area by enabling the use of an embedded transmit/receive (T/R) switch and obviating the need for a separate T/R switch. The proposed HV pulser also incorporates programmable delay elements by which the RTZ time can be controlled. By selecting the minimum allowed value of delay, the pulser is able to generate square‐wave HV pulses as well. Designed and implemented in a 0.18‐μm HV Bipolar‐CMOS‐DMOS (BCD) technology, the pulser occupies a layout area of 0.455 mm2. The function of the proposed design has been verified using post‐layout simulations when driving a 220‐pF capacitor in parallel with a 1‐kΩ resistor load. The simulation results indicate that the pulser consumes an average power of 14.85 mW when producing 2‐MHz, three‐cycle HV pulses with a pulse repetition frequency (PRF) of 5 kHz. [ABSTRACT FROM AUTHOR]