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This paper proposes a design-oriented DC model for MOS transistors in advanced nanometric technologies, based on only six parameters. The proposed model is based on the inversion charge and includes the main short-channel effects for accurately describing the behavior of the transistor DC drain current in all regions (linear to saturation) and regimes of operation (weak to strong inversion). The proposed model is critically compared to existing inversion charge-based models, highlighting the main limitations of previous models presented in the literature and the advantages and disadvantages of our proposal. Then, regarding the model implementation, previously presented inversion charge-based models require a numerical solver to link the transistor’s DC current to its DC node voltages. In this work, we propose an innovative approach to model implementation via the analytical approximation of the Lambert function’s principal branch. Thanks to this approximation, the proposed design-oriented model offers for the first time an analytical single-piece expression of the drain current as an explicit function of the transistor node voltages. The validity of both the proposed transistor DC model and its analytical single-piece implementation is confirmed through simulation and measurement results, using the industrial production-level model UTSOI2 as a reference. The evaluations were conducted on MOS transistors with lengths of 30nm, 60nm, and 150nm in STMicroelectronics 28nm FD-SOI CMOS technology, to validate our results in minimum length, intermediate length, and long transistors in the selected technology. The proposed model achieves an average error of less than 6% in drain current evaluation compared to industry-standard models such as UTSOI2, while significantly reducing computational complexity.

This paper presents a novel charge-based MOSFET model, denoted ACM2, including velocity saturation and drain-induced barrier lowering. Employing the proposed model, all the DC characteristics (currents and charges) and the small-signal equations can be expressed as single-piece expressions valid in all inversion (weak, moderate, and strong) regions. When applied to bulk technology, ACM2 has 5 DC parameters, and an extra parameter is included for SOI technologies to account for back gate bias. Straightforward procedures are provided for extracting the short-channel parameters associated with velocity saturation and back gate bias. Experimental results demonstrate that the DC and small-signal characteristics of the ACM2 model match the silicon measurements in bulk and SOI technologies, with typical errors of less than $20~\%$ in the DC currents and $30~\%$ in the transconductances. The validity of the model is further verified with two design examples. Firstly, simulations of a CMOS inverter in a 130 nm bulk technology show similar results using the PSP or ACM2 models. Then, an RF design example is provided. The ACM2 model is employed to design a 2.4 GHz low-noise-amplifier in a 28 nm FD-SOI CMOS technology. Obtained results in terms of $S_{11}$ , $S_{21}$ , NF, and IIP3 are consistent with simulations using the complete UTSOI2 model provided in the technology design kit.