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Quantum computers are a significant threat to the existing cryptography algorithms. The Saber is a lattice-based post-quantum cryptographic or quantum-safe algorithm designed as a quantum computing attack-resistant protocol. The hardness of SABER is based on the Rounding with Learning (LWR) problem. This work presents a hardware implementation of Striding Toom Cook multiplier-based Saber. SABER is selected algorithms of the NIST (National Institute of Standards and Technology) round 3 criteria. After evaluation in the striding school book multiplier, a technique is also introduced to efficiently load the weighted polynomials into registers and multipliers. The implemented design is realized utilizing Cadence digital-flow (industry-standard) and open-source tool flow (OFRS) with CMOS 180nm TSMC and CMOS (130nm/180nm SKY-WATER) process, respectively. The realized chip for the proposed Saber implementation resulted in an area of 12 mm2 and 43.59 mm2/16 mm2 for TSMC CMOS 180nm and SKY-WATER CMOS 180nm/130nm process, respectively. This implementation provided roughly equal latency for Key encryption, decryption, and Key generation when compared to a state-of-the-art design which utilized different techniques for polynomial multiplication whereas this design utilized 2X, 2X, and 2.5X lesser clock cycles required for Key generation, Key encryption, and decryption, respectively, compared to Saber implementation utilizing Striding Toom cook based multiplier for polynomial multiplication.