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This article presents a process voltage temperature (PVT) -robust ring amplifier that enables a high speed pipelined analog-to-digital-converter (ADC) without gain calibration, operating across a temperature range of 4.6–400 K. To ensure the stability of the ringamp, given the large variation of MOSFET transconductance, threshold voltage, and drain resistance across temperature, we propose a unity-gain-frequency-aware bias calibration and a 1st-stage bias-enhancement technique. The unity-gain-frequency-aware bias calibration stabilizes the amplifier bandwidth by biasing the 3rd stage of the ringamp using a constant- $Gm$ circuit and then optimizing the overall phase margin by tuning the 1st and 2nd stages based on feedback from an amplifier output settling monitor. An additional bias-enhancement technique alleviates the issue of insufficient voltage headroom at cryogenic temperatures (CTs) in the fully differential first stage of the ringamp. This is achieved by separately ac-coupling the NMOS and PMOS of the 1st-stage inverter. Furthermore, to deal with insufficient gain in advanced CMOS process, a cascode correlated-level-shifting (CLS) technique is proposed. This enables gain-calibration-free operation while achieving higher speed than conventional CLS. A 12-bit 250 MS/s pipelined ADC prototype is fabricated with the proposed ringamp in 65 nm CMOS technology. It achieves a signal to noise and distortion ratio (SNDR) above 57.7 dB across the 4.6–400 K temperature range, and Walden figure-of-merit (FoM) of 154 fJ/conv.-step at 4.6 K while operating without any gain calibrations. To the best of our knowledge, the achieved functional temperature range is the widest ever reported for a pipelined ADC.