Search

We analyzed the threshold-voltage dynamic instabilities induced by off-state stress in pseudo-vertical GaN-on-Si Trench mosfets (TMOS). Extensive measurements revealed that off-state stress experiments induce a progressive increase of threshold voltage (VT), that is fully recoverable only after high-temperature cycles, so that it can appear as permanent degradation at room temperature. VT increase is found to be strongly affected by drain bias and negligibly influenced by gate bias (below threshold). Activation energy (EA) extracted from high-temperature VT recovery experiments was determined to be ≈1 eV. We further characterized pseudo-vertical p–n junction diodes fabricated onto the same wafer as the TMOS's by means of capacitance isothermal spectroscopy. This experiment revealed depletion capacitance (CDEP) instabilities with the same EA as that characterizing the VT instability, leading to the conclusion that trap states present in the epitaxy are the cause of both observations. Numerical device simulations guided the physical interpretation of the observed phenomena, i.e., donor traps at 1 eV from the conduction band and localized in the p-layer lead to both VT and CDEP instabilities in the TMOS and in the p–n diode, respectively, by dynamically modulating the effective p-type doping density in the former and the effective depletion layer width in the latter.

In this letter, we investigate the effect of Carbon (C) doping concentration on dynamic RON, vertical leakage and Capacitance-Voltage (C-V) characteristics of p-GaN gate High Electron Mobility Transistors (HEMTs). Measurements performed on state-of-the-art samples show that further increasing C-doping concentration in the GaN buffer above $10^{{19}}$ cm $^{-{3}}$ yields a reduced dynamic-RON degradation, in contrast with the behavior reported in the literature for lower C-doping concentrations. This is confirmed by a complete data set showing a consistent increase in the vertical leakage and in the output capacitance while increasing the C doping, stemming from a less insulating buffer and a reduced 2-DEG depletion, respectively. These observations can be attributed to an increased incorporation of compensating donors leading to a reduction of the net acceptors as the C doping concentration is raised above $10^{{19}}$ cm $^{-{3}}$ .

Dynamic on-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}{)}$ affects the stability of p-GaN power HEMTs. In Schottky-gate HEMTs, dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ is associated to either electron trapping at device surface or dynamic effects occurring in the buffer. However, in p-GaN HEMTs the floating p-GaN region can have an additional role on dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ , due to removal/injection of holes from/into the barrier with relatively long time constants, which can be erroneously interpreted as a reliability issue. In this letter, we present a model to explain the dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ due to surface-related effects in p-GaN power HEMTs. The model, called ‘hole virtual gate’, attributes the experimentally observed ${R}_{ \mathrm{\scriptscriptstyle ON}}$ instability due to negative/positive gate bias stress (NGS/PGS) to the charging/discharging of surface traps in the AlGaN barrier by the removal/injection of holes through the gate metal/p-GaN Schottky junction. We verify the validity of the model by means of calibrated numerical simulations, that correlate the activation energy ${E}_{\text {A}}~\approx ~0.4$ eV of both ${R}_{ \mathrm{\scriptscriptstyle ON}}$ increase/decrease during NGS/PGS to the thermal ionization energy of traps in the barrier.

In this article, we present an analysis of the correlation between interface traps (ITs) and border traps (BTs) on distinctive features of ${C}$ – ${V}$ curves in vertical Al2O3/gallium-nitride (GaN) MOS capacitors. First, pulsed ${C}$ – ${V}$ curves were characterized during the application of quiescent gate bias stresses of different magnitudes and signs. This characterization revealed four main distinctive features: 1) rightward rigid shift; 2) leftward rigid shift; 3) decrease of the $\Delta {C}$ – $\Delta {V}$ slope; and 4) formation of a hump in a gate bias range before the accumulation of electrons at the oxide/semiconductor interface. By means of a combined experimental/simulation analysis, these features were univocally attributed to specific ITs or BTs in the overall trap distribution. The simulation-aided analysis enhances the physical understanding of the ${C}$ – ${V}$ curves features and increases the dependability of the adopted IT measurement technique, allowing for a more rapid process optimization and device technology development.

Application of gallium nitride high-electron-mobility transistors (GaN HEMTs) to millimeter-wave power amplifiers requires gate length scaling below 150 nm: in order to control short-channel effects, the gate-to-channel distance must be decreased, and the device epitaxial structure has to be completely redesigned. A high 2-D electron gas (2DEG) carrier density can be preserved even with a very thin top barrier layer by substituting AlGaN with AlN, InAl(Ga)N, or ScAlN. Moreover, to prevent interaction of hot electrons with compensating impurities and defects in the doped GaN buffer, the latter has to be separated from the channel by a back barrier. Other device designs consist in adopting a graded channel (which controls the electric field) or to adopt nitrogen-polar (N-polar) GaN growth (which decreases the distance between gate and channel, thus attenuating short-channel effects). The aim of this article is to review the various options for controlling short-channel effects, improve off-state characteristics, and reduce drain–source leakage current. Advantages and potential drawbacks of each proposed solution are analyzed in terms of current collapse (CC), dispersion effects, and reliability.