Search

In this work, a charge-based memristor emulator is designed using a single active current mode component Differential Voltage Current Conveyor Transconductance Amplifier with one capacitor and two resistors as passive components. Importantly, the proposed circuit topology can be changed to either grounded or floating configuration using a single switch. Moreover, the proposed memristor design can be operated either in incremental or decremental configuration by using another switch. Therefore, using only two switches, the same circuitry can be utilized to design the floating/grounded incremental/decremental memristor. The pinched hysteresis loop area can be controlled by applying different biasing voltages. Further, the mathematical analysis is performed to drive the theoretical TiO2 based results for the proposed memristor emulator. In addition, simulations confirming the theoretical analysis are conducted in PSPICE using the 180 nm TSMC technology with a supply voltage of ± 0.9 V by varying frequencies and capacitances to obtain a pinched hysteresis loop. The presented circuit performs effectively for frequencies upto 500 MHz while operating with grounded type memristor and 300 MHz with floating type design. To check the ability to remember the history of the proposed memristor, the non-volatility test is performed for both the incremental and decremental configurations. Moreover, the suggested memristor design is applied in an adaptive learning circuit to prove its feasibility in neuromorphic applications. [ABSTRACT FROM AUTHOR]

This paper presents a current-mode VCSEL driver (CMVD) implemented using 180 nm CMOS technology for application in short-range LiDAR sensors, in which current-steering logic is suggested to deliver modulation currents from 0.1 to 10 mApp and a bias current of 0.1 mA simultaneously to the VCSEL diode. For the simulations, the VCSEL diode is modeled with a 1.6 V forward-bias voltage and a 50 Ω series resistor. The post-layout simulations of the proposed CMVD clearly demonstrate large output pulses and eye-diagrams. Measurements of the CMVD demonstrate large output pulses, confirming the simulation results. The chip consumes a maximum of 11 mW from a 3.3 V supply, and the core occupies an area of 0.1 mm2. [ABSTRACT FROM AUTHOR]

The work examines the main technical indicators of electromechanical converters callers with levitation elements, a generalized design method has been developed tions, as well as design diagrams and functional dependencies of the main varieties of electromechanical devices with elements of levitation. Analytical expressions for the levitation coefficient as a function of the dimensions of the magnetic core and coefficient factor of force multiplicity, technical characteristics of levitation material element, set superheat temperature. A mathematical model has been compiled for based on the parameters of the current mode and forces from the equations of electrical, magnetic, mechanical and thermal circuits of the magnetic system. As a result, the main dimensions of the magnetic system and dimensionless quantities. Analytic expressions for the main dimensions, the specified values of the winding overheating temperature are taken into account, input and output parameters, the condition of uniformity of the magnetic field in the working air nom gap. The optimal values of the dimensions of the magnetic circuit, active resistors have been determined winding voltages are minimal, resulting in minimization of losses active capacities. [ABSTRACT FROM AUTHOR]

Log and Antilog Amplifiers are two very important functions in many electronic devices. Thus, in this article a new current mode (CM) log and antilog amplifier using current follower transconductance amplifier (CFTA) are presented. The logarithmic circuit is constructed using only one CFTA as active elements and one metal oxide semiconductor (MOS) transistor as diode operation and antilogarithmic amplifier circuit is implemented using only one CFTA as the active component, one MOS transistor as diode operation and two MOS transistor as active resistors. It provides the advantage of using MOS transistor instead of a resistor and diode that is beneficial to IC implementation in terms of space consideration which are suitable for IC implementation. These circuits provide logarithmic and antilogarithmic responses. Additionally, there is no demand to set selection criteria for components. The operation of the circuit in the current mode was verified by a nonideality study. PSPICE was used to test the scheme's functioning. The output curves coincide very close with the theoretical expectation. [ABSTRACT FROM AUTHOR]

This paper presents a novel low-voltage low power fully differential class AB current output stage with high linearity and unique current drive capability. The proposed circuit is based on a simple and efficient structure to obtain high linearity by minimising the channel length modulation effect and also avoids cascade structure to act best in low-voltage applications. Giving the complete analyses and equations of the circuit, its properties are verified by Cadence using TSMC 0.18 µm CMOS parameters. In order to study its performance at the presence of non-idealities, Pre-layout and Post-layout both plus Monte–Carlo simulations are also performed. Under±0.9 V supply and 35 µA output bias current, it can deliver the ever high output current of ±350 mA with THD of −49 dB and output impedance of 2.8 MΩ, which leads to a unique high current drive ratio (Ioutmax/Ibias) of 10,000 and low consumed power of 150 µw in pre-layout simulation. In post-layout plus Monte–Carlo simulation, the results will be as ±320 mA output current, −42 dB THD, 2.2 MΩ output impedance, 40 µA DC current of the output branch, 8000 current drive ratio and 160 µw consumed power. These remarkable results prove the proposed novel COS not only as the unique one in the world but Longley ahead of the yet second rank COS by some unbeatable ratios as 11300×,14×,4× and3× in FT, Ioutmax, (Ioutmax/power), and current drive, respectively, that promise to keep it as the lead one for many years in low-voltage/power ultra-high current applications. [ABSTRACT FROM AUTHOR]

Recent developments in multiplication circuits with fewer transistors, higher speed, and reduced energy consumption are lowering hardware costs. Approximate multiplication is used for fault-tolerant applications, such as image and signal processing. These applications offer considerable improvement at the cost of reduced accuracy. Compressors are the main component of any multiplier structure. In this work, the design of an approximate multiplier based on current mode, using 4:2 and 5:2 approximate compressors and current over scaling technique is suggested to reduce power consumption, delay, and hardware components compared to existing architectures. In the proposed approach for the design of compressor circuits, current mode binary converters with 32 nm CNTFET technology are used. This work is done in three steps: (1) converting input currents into voltage and creating multi-level voltages. (2) Implementing voltage level detector. (3) Generation of output current based on threshold voltage. The proposed technique uses less number of transistors. The simulation was done under HSPICE software and the efficiency of the compressors was compared in terms of delay, power, and power delay product (PDP). Based on the simulation results, the PDP value for 4:2 and 5:2 compressor circuits is calculated as 0.0097 and 0.0131 fJ, respectively. Then, an approximate multiplication of 8 × 8 using these compressors is designed for multiplying images under MATLAB software. This multiplier has achieved a good improvement in terms of PSNR and MSSIM (respectively 9.14 and 2.85%) compared to advanced approximate multipliers. Also, the proposed approach performs better in terms of accuracy, power consumption, and delay. [ABSTRACT FROM AUTHOR]

The relationship between the amount of energy consumption and the circuit speed to change the design efficiency is an important challenge in designing digital circuits. Adders are essential components of computing circuits that play an important role in computing speed. This article proposed a new design for a single-bit current mode full adder using the field effect transistors based on carbon nanotubes to enhance the speed and reduce the occupied space on the chip. The correct combination of the majority function, the current mirror technique, and the sum value on carry reduced the delay of all adder circuits. The simulations have been done by HSPICE software and based on the provided standard model of 32 nm with CNTFET technology. The proposed design has improved by 55% in terms of delay. The PDP level in the proposed design has decreased by 63% compared to the previous designs. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

An adaptive biased architecture of voltage differencing transconductance amplifier (AB-VDTA) with high transconductance gain is proposed in this paper. The proposed AB-VDTA is very efficient in terms of power. The structure proposed involves of two units namely two transconductance amplifiers (TAs) and two squarer. The bias current of the TA is made to vary with a square relation of the differential input voltage. Therefore, the proposed structure provides tunable gain depending on the input differential voltage. The proposed AB-VDTA exhibits improved transconductance gain, transient characteristics, reduced standby power dissipation and linearity for large range of inputs. The mathematical formulation has been presented to establish the characteristics of the proposed AB-VDTA. The proposed structure of AB-VDTA is validated through SPICE simulations using 180 nm complementary metal oxide semiconductor (CMOS) technology. The proposed scheme has an edge over the existing ones as the outlined methods enhance the transconductance gain by increasing the bias current. The g m 1 values are observed to be 2.3 and 1.4 mS for proposed AB-VDTA and conventional VDTA, respectively, with the corresponding 3 dB frequencies 620 and 348 MHz. Therefore, 64% improvement in transconductance gain is recorded for same value of bias currents. The linear input range of TA1 is observed to be ± 1 5 0 mV and the overall linear range of the VDTA is ± 1 0 0 mV for the proposed AB-VDTA. The PVT analysis is carried out to show the effect of process corners. To check the robustness of the proposed VDTA, Monte Carlo analysis is performed, and results have been included in the form of histograms. As an application example, a current mode (CM) universal single input multiple output (SIMO) biquad filter is also designed using the proposed VDTA to show its usefulness, and a 2.7 times higher pole frequency is obtained at equal bias current. [ABSTRACT FROM AUTHOR]

This communication presents two new first order universal active filter configurations employing operational transconductance amplifiers (OTA) and use grounded capacitor which is prominently suitable for integrated chip (IC) fabrication. One of the proposed topologies provides voltage mode (VM) and transconductance mode (TCM) of operations while the other circuit provides current mode (CM) in addition with transresistance mode (TRM) filter functions. All three first order filter functions namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) are configurable with appropriate choice(s) of input voltage/current signals. An equal transconductor condition (which can be easily achieved) is required for the realization of APF functions. The proposed filter configurations possess high input impedance and high output impedance and also offer independent electronic tunability of pole frequency/cut-off frequency. The gain of filters realized in VM, TCM and TRM has independent electronic tunability feature and can be adjusted through transconductor. For the usability of proposed filters, multi-phase sinusoidal oscillator has also been demonstrated. To assure the workability of the proposed filter structures, PSPICE simulations with CMOS OTA implemented in 0.18 µm TSMC technology parameters has been used. Various simulation results including Monte-Carlo simulations, process corner analysis, total harmonic distortions (%THD) and temperature analysis have also been appended. Experimental results employing off-the-shelf IC LM13700 type OTAs have also been included to verify the theoretical propositions of first order universal filters and multiphase sinusoidal oscillators. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper presents a current-mode VCSEL driver (CMVD) implemented using 180 nm CMOS technology for application in short-range LiDAR sensors, in which current-steering logic is suggested to deliver modulation currents from 0.1 to 10 mApp and a bias current of 0.1 mA simultaneously to the VCSEL diode. For the simulations, the VCSEL diode is modeled with a 1.6 V forward-bias voltage and a 50 Ω series resistor. The post-layout simulations of the proposed CMVD clearly demonstrate large output pulses and eye-diagrams. Measurements of the CMVD demonstrate large output pulses, confirming the simulation results. The chip consumes a maximum of 11 mW from a 3.3 V supply, and the core occupies an area of 0.1 mm2.

MCNP radiation transport output is post-processed by DRiFT, a D etector R esponse F unction T oolkit to simulate detailed nuclear instrumentation response. DRiFT can be used to assess the performance and potential limitations of scintillator, gas, and semiconductor detectors under a variety of simulated conditions not easily achievable in a laboratory setting. This work describes new updates in DRiFT for scintillator simulations which focus on the capability to simulate scintillators in current mode, an expansion of trigger options, and the ability to customize individual detector properties in a simulation. These improvements are designed to facilitate the ability to model large arrays of scintillator detectors with higher fidelity than was previously possible and are demonstrated in three examples. The first shows the difference between operating DRiFT in current and pulse mode. In the second example, which is intended to demonstrate deviations in individual detector performance, each detector has properties (PMT gain, optical transport, scintillation yield, etc.) that vary between detectors and are specified in DRiFT. A final example examines how DRiFT could be used to optimize digitizer settings in high rate measurements with split signals using the new common trigger option. • The ability to simulate current mode experiments has been implemented in DRriFT. • New features include common triggers and the ability to assign individual scintillator, PMT, and digitizer properties. • New features are demonstrated in several examples with scintillator arrays. [ABSTRACT FROM AUTHOR]

This study introduces a wideband LNTA-based receiver employing full current mode (FCM) signal transmission, leveraging a broadband and highly linear current-mode analog baseband (CMAB). The CMAB module comprises a shunt feedback low pass filter and a programmable gain amplifier (PGA) with wide bandwidth, utilizing a regulated CG current mirror design, enriched by gm-boosting methodology and positive feedback capacitance reutilization through an identical boost amplifier. Fabricated in 12 nm FinFET CMOS process, the FCM receiver attains notable characteristics including a baseband bandwidth of 1 GHz, a conversion gain of 30 dB, a noise figure of 5.2 dB, and an OIP3 of 14.6 dBm, while operating with a low supply voltage of merely 0.9 V. Simulation results validate the efficacy of this FCM receiver for wideband communication, effectively addressing the linearity constraints associated with low supply voltages and maximizing the advantages of FinFET technology in current-mode signal transmission. The total layout area is 0.484 mm 2. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient CMOS image sensor (CIS) for always-on object detection by using 1-bit log-gradient feature extraction in analog current domain. Compared with traditional image sensors with high-resolution ADCs, the proposed CIS extracts gradients in ratio form and generates feature maps at 1-bit resolution, which eliminates unnecessary background information and illumination-related data, and reduces the data computation in the later detector. The system containing the proposed CIS and back-end ANN detector is modeled with python and the simulation achieves an accuracy of 93.2 % for person detection. The CIS employs current mode divider and comparator to compute the gradient ratios. An accurate and configurable muti-input and muti-output (MIMO) current divider is proposed, composed of two cascaded modified second generation current controlled conveyors (M-CCCIIs). The proposed CIS was fabricated in a 0.18 μm standard CMOS process and realized a frame rate of 170 fps and an energy efficiency of 337 pJ/pixel in a power consumption of 1.1 mW. Experimental results show that the proposed CIS can realize the function of extracting log-gradients. [ABSTRACT FROM AUTHOR]