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Low-frequency (LF) noise measurements are compared for Schottky-gate AlGaN/GaN heterostructure planar and fin field-effect transistors (FinFETs) as functions of gate voltage and measuring temperature. The noise of each device type is consistent with a carrier number fluctuation model. Similar effective defect-energy Eo distributions are derived for each of the two device architectures from measurements of excess drain-voltage noise-power spectral density vs temperature from 80 to 380 K. Defect- and/or impurity-related peaks are observed in the inferred energy distributions for Eo < 0.2 eV, Eo ≈ 0.45 eV, and Eo > 0.6 eV. Significant contributions to the LF noise are inferred for nitrogen vacancies and ON and FeGa impurity complexes. Ga dangling bonds at fin interfaces with gate metal are likely candidates for enhanced noise observed in FinFETs, relative to planar devices. Reducing the concentrations of these defects and impurity complexes should reduce the LF noise and enhance the performance, reliability, and radiation tolerance of GaN-based high electron mobility transistors. [ABSTRACT FROM AUTHOR]

N-type carbon nanotubes (CNTs)-based field-effect transistors (FETs) have huge potential applications in low-power consumption tunnel FETs. However, the low-work function metal electrodes can achieve n-type CNTs, but they are easily oxidized due to poor environmental stability. Therefore, based on first-principles calculations, we proposed halide perovskite nanowires Cs4MX5 (M = Pb, Sn; X = Cl, Br, I) inner filling to achieve n-type single-walled CNTs (SWCNTs). The results indicated that all the perovskite nanowires located at the center of the SWCNTs possess high stability. Moreover, the diameter of SWCNTs is a crucial factor affecting the inner filling of perovskite nanowires with an optimal diameter of about 1.4 nm. Furthermore, all the perovskite nanowires Cs4MX5 are excellent electron donors, and the largest charge transfer is up to 1.72 e/nm for Cs4SnI5. Their interaction mechanism reveals that the low work function and the large internal bandgap are two important factors for cubic-phase nanowires to realize the n-type CNTs. Our findings provide some candidate materials and a feasible way to achieve n-type CNTs for applying CNTs-based FETs. [ABSTRACT FROM AUTHOR]

We investigate the MX2 (M = {Hf, Zr}, X = {S, Se}) transition metal dichalcogenides patterned into armchair (AC) and zigzag (ZZ) nanoribbons (NRs) as potential channel materials in future logic field-effect devices. Ab initio quantum transport simulations are employed to assess the electronic, transport, and ballistic field-effect transistor (FET) properties of devices with such quasi-one-dimensional channels. We report a non-monotonic scaling behavior of MX2NR properties due to strong quantum confinement effects, which is reflected in a strong dependence of the ON-state current (ION) of MX2NR FETs on the nanoribbon configuration. The ∼2 nm-wide HfSe2 and ZrSe2 AC-PFETs have the highest ION of up to 2.6 mA/μm at 10 nA/μm OFF-state current. Surprisingly, MX2NR ZZ-NFETs exhibit a current increase of up to 70% when channel width is scaled down, with ION reaching 2.2 mA/μm in ∼2 nm-wide devices. The high ON-state performance is a direct consequence of high carrier injection velocity, which is explained by analyzing the band structure, transmission, and density of states. We demonstrate that nanostructured MX2 materials can be promising candidates for future logic transistors based on multi-nanowire architectures. [ABSTRACT FROM AUTHOR]

The deep-level drain current transient spectroscopy (Id-DLTS) measurements of Al -doped SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) strongly suggest that the reduction in the channel mobility at low temperatures is related to a shallow trap detectable at 70 K. Using the Shockley–Reed–Hall (SRH) theory, the level of this trap has been extracted to be around 0.15 eV below the conduction band minimum of SiC. Density functional theory (DFT) calculations of Al Si N C Al Si and Al Si O C Al Si defect complexes have found one configuration of the Al Si O C Al Si complex, which has a charge transition level within the SRH extracted trap level range. Therefore, we suggest that these Al Si O C Al Si defects are likely candidates for traps responsible for the channel mobility reduction. [ABSTRACT FROM AUTHOR]

Large Schottky barriers formed at the interfaces between graphene and 2D semiconductors often degrade device performance. Here, taking the Janus MoSO as a prototype and using the first-principles calculations together with the band unfolding technique, we demonstrate that the Ohmic contact (OC), which is absent in pristine graphene/MoXY (X/Y = S, Se, Te. X ≠ Y), is realized in the pristine graphene/MoSO (G/MoSO) heterostructure. G/OMoS shows the n -type OC (OC- n) that leads to the p -doping of the graphene layer with a hole density of 1.17 × 10 13 /cm 2 , while G/SMoO exhibits the p -type Schottky contact with a tunable Schottky barrier height. The realization of OC and the interface dependent contact type are mainly attributed to the large intrinsic dipole between asymmetric S and O layers, which dominate the different behaviors of charge transfer and the associated interface dipole in heterostructures. Inspired by the finding, considering the larger dipole moment in Janus MoSeO and MoTeO, we further confirm that both OC- n and OC- p exist in pristine G/MoSeO and G/MoTeO. Moreover, on comparison with MoSO, both G/OMoS and G/SMoO show enhanced optical absorptions (∼ 10 5 cm − 1 ) in most of the visible light range. Our results not only show the potential application of G/MoSO in nanoelectronic devices such as field-effect transistors but also indicate that dipole engineering would help us to predict or design desirable electric contacts of Janus-transition metal dichalcogenide-based metal/semiconductor systems in advance. [ABSTRACT FROM AUTHOR]

The successful synthesis and discovery of unique properties in two-dimensional Janus materials have positioned them as promising candidates for applications in sensors, field-effect transistors, and ultrasensitive detectors. In this study, we utilized first-principles calculations to predict a novel Janus CeIBr monolayer. Our calculations show that Janus CeIBr monolayer behaves as a bipolar magnetic semiconductor, demonstrating both mechanical and thermodynamic stability, along with a high Curie temperature of 242 K and in-plane magnetic anisotropy (102.92 meV). A notable intrinsic valley splitting of 66 meV is also evident in CeIBr, highlighting its distinctive valley contrast characteristic. Furthermore, the application of biaxial strain effectively transforms the magnetic ground state of CeIBr from a ferromagnetic state to an antiferromagnetic state and alters the direction of the easy magnetization axis from in-plane to out-of-plane. Our findings offer a theoretical foundation for the design of novel anomalous valley Hall effect-based electronic devices utilizing the Janus CeIBr monolayer. [ABSTRACT FROM AUTHOR]

Carbon nanotubes have shown great promise for high-performance, large-area, solution processable field-effect transistors due to their exceptional charge transport properties. In this study, we utilize the spin-coating method to form networks from selectively sorted semiconducting single-walled carbon nanotubes (s-SWNTs), aiming for scalable electronic device fabrication. The one-dimensional nature of s-SWNTs, however, introduces significant roughness and charge trap sites, hindering charge transport due to the van der Waals gap (∼0.32 nm) between nanotubes. Addressing this, we explored the effects of anion doping on the spin-coated s-SWNT random network, with a focus on the influence of the small size of halogen anions (0.13–0.22 nm) on these electronic properties. Raman and ultraviolet–visible–near-infrared optical spectroscopy results indicate that smaller anions significantly enhance doping effects through strong non-covalent anion–π interactions, improving charge transport and carrier injection efficiency in s-SWNTs, especially for n-type operation. This improvement is inversely proportional to the size of the halogen anions, with the smallest anion (fluorine) effectively transitioning the electrical characteristics of the s-SWNT network from ambipolar to n-type by reducing both junction and contact resistances through anion doping, based on anion–π interaction. [ABSTRACT FROM AUTHOR]

The two-dimensional (2D) Ruddlesden−Popper phase all-inorganic halide perovskite Cs2PbI2Cl2 has attracted tremendous attention because of its high carrier mobility, strong light-absorbing ability, and excellent environmental stability, possessing enormous potential for use as a high-performance optoelectronic device. Here, we present two transistor devices based on monolayer (ML) Cs2PbI2Cl2 and reveal their performance and current transport mechanisms through ab initio quantum transport calculations. The n-type 10 nm metal-oxide-semiconductor field-effect transistor shows a high on-state current Ion of 3160 μA/μm, and excellent performance regarding subthreshold swing, intrinsic delay time (τ), and power consumption, which completely match the International Roadmap for Device and Systems (2021 version) targets for high-performance devices and low-power devices in 2028. Moreover, phototransistors based on monolayer Cs2PbI2Cl2 also display a strong response to UV light, with a light-to-dark current ratio reaching a maximum of 104. Meanwhile, a high specific detectivity of 2.45 × 1011 Jones is obtained. The results of our study suggest that ML Cs2PbI2Cl2 is a promising candidate for high-performance transistors. [ABSTRACT FROM AUTHOR]

4H-SiC/ SiO 2 interface states play a major role in the performance and reliability of modern 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs). To gain new insights into these interface states, we developed a cryogenic measurement technique that uses photon-assisted electron depopulation to probe device performance limiting 4H-SiC/ SiO 2 interface states. This technique enables the characterization of shallow as well as deep states at the 4H-SiC/ SiO 2 interface of fully processed devices using a cryogenic probe station. Our method is performed on n-channel 4H-SiC MOSFET test structures with deposited oxide and postoxidation anneal. We identify conditions under which the electrons remain trapped at 4H-SiC/ SiO 2 interface states and trigger the controlled photon-assisted electron depopulation within a range of photon energies. This allows us to prove the presence of near interface traps, which have previously been found in thermally grown 4H-SiC MOS structures. Our results are supported by device simulations. Additionally, we study the impact of irradiation intensity and light exposure time on the photon-induced processes. [ABSTRACT FROM AUTHOR]

We propose a main mechanism of large valley splitting experimentally observed at the interface of buried oxide (BOX)/silicon-on-insulator (SOI) structures. Silicon metal-oxide-semiconductor field effect transistors fabricated on a SIMOX (001) substrate, which is a kind of the SOI substrate, that is annealed at high temperatures for a long time are known to exhibit large valley splitting, but the origin of this splitting has long been unknown. Extended zone effective-mass approximation predicts that strain significantly affects valley splitting. In this study, we analyzed valley splitting based on this theory and found that the shear strain along [110] of approximately 5% near the BOX interface is a promising source for large valley splitting. [ABSTRACT FROM AUTHOR]

The ultra-wide bandgap of gallium oxide provides a rich plethora of electrically active defects. Understanding and controlling such defects is of crucial importance in mature device processing. Deep-level transient spectroscopy is one of the most sensitive techniques for measuring electrically active defects in semiconductors and, hence, a key technique for progress toward gallium oxide-based components, including Schottky barrier diodes and field-effect transistors. However, deep-level transient spectroscopy does not provide chemical or configurational information about the defect signature and must, therefore, be combined with other experimental techniques or theoretical modeling to gain a deeper understanding of the defect physics. Here, we discuss the current status regarding the identification of electrically active defects in beta-phase gallium oxide, as observed by deep-level transient spectroscopy and supported by first-principles defect calculations based on the density functional theory. We also discuss the coordinated use of the experiment and theory as a powerful approach for studying electrically active defects and highlight some of the interesting but challenging issues related to the characterization and control of defects in this fascinating material. [ABSTRACT FROM AUTHOR]

In this paper, the p-GaN gate AlGaN/GaN high electron mobility transistors (HEMTs) with varying combinations of gate metal work function and gate geometry are fabricated and investigate the influence of gate leakage current (IGS) on the threshold voltage (VTH) and subthreshold swing (SS). The unique dependence of VTH and SS on gate geometry for different metals is observed, which is different from traditional field-effect transistors. A novel hybrid physics model, consisting of the traditional capacitance divider model and hole injection model, is proposed to explain this phenomenon, and the results exhibit an excellent agreement with the experimental data. The holes traverse the gate/p-GaN Schottky barrier by thermal emission or tunneling and inject into the p-GaN layer, generating the IGS. Expanding upon the traditional capacitance divider model, a portion of the injected holes accumulate at the p-GaN/AlGaN interface and induce the corresponding electrons at the AlGaN/GaN heterojunction, which promotes channel conduction. Hence, the transfer curves display the correlation between IGS and VTH as well as SS. The results show that high IGS can alleviate the instability of VTH caused by the lithographic overlay error, and simultaneously optimize SS. This work offers a novel perspective for examining the turn-on mechanism of p-GaN HEMTs, thereby contributing to device design. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a hydrogen-terminated diamond (H-diamond) field-effect transistor (FET) with Al2O3/CeB6 gate materials. The CeB6 and Al2O3 films have been deposited by electron beam evaporation technique, sequentially. For the 4/8/12/15 μm gate length (LG) devices, the whole devices demonstrate distinct p-type normally off characteristics, and all the threshold voltage are negative; all the absolute values of leakage current density are 10−4 A/cm2 at a VGS of −11 V, exhibiting a relatively low leakage current density compared with CeB6 FETs, and this further demonstrates the feasibility of the introduction of Al2O3 to reduce the leakage current density; the maximum drain–source current density is −114.6, −96.0, −80.9, and −73.7 mA/mm, which may be benefited from the well-protected channel. For the 12 μm LG devices, the saturation carrier mobility is 593.6 cm2/V s, demonstrating a good channel transport characteristic. This work may provide a promising strategy for the application of normally off H-diamond FETs significantly. [ABSTRACT FROM AUTHOR]

Molybdenum disulfide (MoS2), a semiconducting two-dimensional layered transition metal dichalcogenide (2D TMDC), with attractive properties enables the opening of a new electronics era beyond Si. However, the notoriously high contact resistance (RC) regardless of the electrode metal has been a major challenge in the practical applications of MoS2-based electronics. Moreover, it is difficult to lower RC because the conventional doping technique is unsuitable for MoS2 due to its ultrathin nature. Therefore, the metal–insulator–semiconductor (MIS) architecture has been proposed as a method to fabricate a reliable and stable contact with low RC. Herein, we introduce a strategy to fabricate MIS contact based on atomic layer deposition (ALD) to dramatically reduce the RC of single-layer MoS2 field effect transistors (FETs). We utilize ALD Al2O3 as an interlayer for the MIS contact of bottom-gated MoS2 FETs. Based on the Langmuir isotherm, the uniformity of ALD Al2O3 films on MoS2 can be increased by modulating the precursor injection pressures even at low temperatures of 150 °C. We discovered, for the first time, that film uniformity critically affects RC without altering the film thickness. Additionally, we can add functionality to the uniform interlayer by adopting isopropyl alcohol (IPA) as an oxidant. Tunneling resistance across the MIS contact is lowered by n-type doping of MoS2 induced by IPA as the oxidant in the ALD process. Through a highly uniform interlayer combined with strong doping, the contact resistance is improved by more than two orders of magnitude compared to that of other MoS2 FETs fabricated in this study. [ABSTRACT FROM AUTHOR]

The rising temperature due to a self-heating or thermal environment not only degrades the subthreshold performance but also intensifies thermal stress, posing a severe challenge to device performance and reliability design. The thermal stress effects on the ON-state performance of the p-type fin field-effect transistor were previously studied. However, as far as we know, how thermal stress affects its subthreshold conduction remains unclear, which is studied in this manuscript. The impact of thermal stress due to the self-heating of adjacent devices on subthreshold conduction is investigated by solving the quantum transport, thermal conduction, and force balance equations for ballistic transport and dissipative transport with phonon scattering. Then, the thermal stress effects at different ambient temperatures are further discussed and analyzed. The simulation results show that the OFF-state leakage current can be reduced by thermal stress, even up to 9.28% for the (110)/[001] device operating at an ambient temperature of 550 K, and its reduction is the comprehensive result of the thermal stress effects on the band structure, potential profile, carrier distribution, and source-to-drain tunneling. In addition, the thermal stress has no significant effects on subthreshold swing although it can change the magnitude of the subthreshold current. Moreover, the effect of thermal stress on subthreshold conduction is highly dependent on the thermal environment of the device and the crystal orientation of the channel semiconductor material. [ABSTRACT FROM AUTHOR]

The performance of SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs) degrades seriously after a period of continuous operation. To directly understand this issue, we conduct real-time time-dependent density functional theory (TDDFT) simulations on a series of nitrogen passivated SiC– SiO 2 interfaces to monitor the interaction between carriers and interface atoms. We find that the nitrogen passivation always leaves behind two local states near the VBM, which gives a chance to the strong interaction between channel carriers and C–N bonds, and finally results in the generation of C dangling bond defects. These processes are vividly presented and confirmed by the TDDFT simulation. Additionally, the results show that the new defects are more easily formed by the passivated C cluster than the passivated Si vacancy. These studies provide physical insights into the degradation mechanisms of working SiC MOSFETs, while simultaneously demonstrating the advantage of TDDFT as a crucial tool for investigating defect generation dynamics in semiconductor devices. [ABSTRACT FROM AUTHOR]

Gallenene is a novel metallic 2D material that can provide a semiconducting counterpart if patterned into quasi-one-dimensional (quasi-1D) nanostructures, i.e., gallenene nanoribbons (GaNRs). We investigate semiconducting GaNRs as a potential channel material for future ultrascaled field-effect transistors (FETs) by employing quantum transport simulations based on Green's functions and tight-binding Hamiltonians with the orbital resolution calibrated on ab initio calculations. The impact of GaNR width downscaling from ∼6 nm down to ∼0.2 nm on the electronic, transport, and ballistic device properties is investigated for the FET channel length of 15 nm. We report current enhancement and injection velocity overshoot effects for sub-1.2 nm-wide nFETs and pFETs, with a maximum current increase of 53% in the 1.2 nm-wide GaNR pFET in comparison to the widest device. In addition, promising current-driving capabilities of n- and p-channel GaNR FETs are observed with top ballistic currents of more than 2.2 mA/μm and injection velocities of up to 2.4 × 107 cm/s. The reported data are explained by analyzing the evolution of band structure and related parameters such as injection velocity, quantum capacitance, effective transport mass etc., with increasing quantum confinement effects in ultranarrow GaNRs. Generally, we find that quasi-1D gallenene is a promising channel material for future nanoscale FETs, especially for transistor architectures based on stacked nanosheets. [ABSTRACT FROM AUTHOR]

Negative differential resistance (NDR) is observed in various emerging electronic devices. As compared to the conventional silicon-based field effect transistor (FET), the NDR is widely investigated in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs. In this work, we study the NDR effect for the TMD-based metal-edge-contact MoS 2 double-gate FET with 10 nm channel length. The multiscale atomistic simulation is demonstrated for the lateral heterostructure of a metal–semiconductor–metal FET by density functional theory, maximally localized Wannier function tight-binding Hamiltonian, and non-equilibrium Green's function methods. The quantum transport model in the given lateral heterostructure resulted in NDR in a double-gate FET. Here, we focus on the NDR by the systematic study of the transmission spectrum of the metal-edge-contact MoS 2 channel FET and finally compare it with zero NDR ideal highly doped FET. The peak-to-valley ratio in the NDR response can be modulated with the change in the gate-to-source voltage and can be used to explore various future electronic applications. [ABSTRACT FROM AUTHOR]

With the proportional reduction of metal–oxide–semiconductor field effect transistor (MOSFET) devices, the short channel effect, the parasitic effect, and the field strength effect are significantly enhanced, the proportion of parasitic resistance increases, and the non-intrinsic noise also increases, which seriously affects the working efficiency of the device. However, existing research mainly focuses on the intrinsic noise of MOSFET, and there is little research on the non-intrinsic noise; furthermore, the models describing the relationship between non-intrinsic noise, device structure, and bias have not yet been addressed. Therefore, in this paper, 90, 65, 32, 10, and 5 nm MOSFETs are studied. The rate of the intrinsic ballistic parameter is introduced to set up the source–drain current model and the non-intrinsic noise model. The source–drain current model is consistent with the theoretical model, numerical simulation, and experimental results in the literature. Finally, the relationship between the non-intrinsic noise and the bias and the device parameters are analyzed, and the conclusion is helpful to improve the working efficiency, lifetime, and response speed of nanoscale MOSFET devices. [ABSTRACT FROM AUTHOR]

Gallium oxide (G a 2 O 3 ) is a promising ultra-wide bandgap material offering a large bandgap (> --> 4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga 2 O 3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga 2 O 3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga 2 O 3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga 2 O 3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga 2 O 3 power transistors. [ABSTRACT FROM AUTHOR]

The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a two-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all FeSQUID-based cryogenic computer, ensuring minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process. [ABSTRACT FROM AUTHOR]

In this paper, two substrate optimization approaches for triple stacked nanosheet field-effect transistors (SNSHFETs), namely the optimization of buried oxide and the selective deposition of punch-through-stopper (PTS) substrate, have been examined, and simulations have been carried out using technology computer-aided software. A comprehensive study of the leakage current and key electrical characteristics (I ON, V T, subthreshold swing, drain-induced barrier lowering) has also been performed based on variations in temperature from 298 K to 450 K, sheet width, fin pitch, substrate width, and source/drain doping, as well as different substrates. When the ambient temperature of the SNSHFET is varied from 298 K to 450 K, the gate-induced drain leakage (GIDL) current increases and degrades the V T and I ON/ I OFF ratio. The GIDL current also increases with increased doping of the source and drain. The impact of ultra-thin body substrate in the SNSHFET is also studied for the reduction in GIDL current and optimization in the performance. It is observed that a reduction in the substrate width and the nanosheet width decreases the GIDL current, while variation in the inter-fin pitch has no significant impact on the GIDL current and other electrical characteristics. The band-to-band tunneling rate and electric field profiles are observed in the channel–drain and gate–substrate overlap regions to understand the physical insights of leakage current in the SNSHFET. This work also clarifies the dependency of the GIDL current on the gate and drain voltage supply, respectively. In addition, how the GIDL current responds to the variation in the source–drain doping and with different PTS doping has been explained. A 3 nm SNSHFET is designed and its electrical and GIDL characteristics are compared with those of novel devices such as the forksheet FET and complementary FET. [ABSTRACT FROM AUTHOR]

Hysteresis window observed in ferroelectric negative capacitance field-effect transistors (NCFETs) have been a persistent challenge in the development of reliable logic circuits, often leading to abnormal operational conditions. Despite its significance, the underlying factors driving this hysteresis phenomenon remain elusive. In this study, we employ the quasi-static L–K equation in conjunction with the Mott–Gurney law to study the impact of VO++ migration on the hysteresis behavior of NCFETs, based on a surface potential-based physical model. Compared with pristine NCFET, the difference of peak voltages in value of 1.3 V was achieved in VO++-involved sample upon reverse and forwards scanning. This result clearly suggests that the relaxation of charged oxygen vacancies significantly affects the threshold voltage under applied sweeping voltages, providing a plausible explanation for the emergence of hysteresis windows in NCFETs. A replacement of the conventional oxide layer with a buffer layer containing high-mobility ions is proposed to adjust the hysteresis window. Importantly, in accordance with the theoretical predictions, the increased ion mobility results in a substantial reduction in the hysteresis window observed in NCFETs. Our proposed physical mechanism, elucidating the space-charge-induced hysteresis behavior, provides fresh insights for mitigating hysteresis effects, thereby advancing the potential applications of NCFETs in logic circuits. [ABSTRACT FROM AUTHOR]

With the capability of in-memory computing, integrated nonvolatile logic devices can mitigate the back-and-forth movement of data between storage and logic units, thus effectively enhancing computational speed and reducing power consumption. In this work, two-dimensional (2D) CuInP2S6, which reveals robust polarization within a few nanometer thicknesses, was utilized as gate dielectric for ferroelectric field effect transistor (FeFET). Device with a ReS2 channel demonstrated a high on/off ratio of current of 105, accompanied by a substantial hysteresis window of 2.8 V. Additionally, ReS2 FETs, gated with an h-BN layer, exhibited a switch ratio of 108 and minimal hysteresis of 61.6 mV at room temperature, attributed to the atomically flat heterointerface with negligible traps. Leveraging the performance of these devices enabled the creation of a nonvolatile logic inverter, wherein the ReS2/h-BN FET acts as the load transistor, and ReS2/h-BN/CIPS FeFET serves as the driving unit. This configuration stably operates with low power consumption of 0.45 μW and outstanding retention exceeding 1000 s. This work presents a viable device architecture for designing nonvolatile logic circuits applicable in in-memory computing. [ABSTRACT FROM AUTHOR]

The development of complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) based on two-dimensional (2D) materials offers an important opportunity to reduce static power and increase the integration density of integrated circuits. One promising approach to realize these CMOSFETs is to employ ambipolar 2D materials as channel materials with designed device structure to control the carrier transport properties for CMOSFET characteristics. However, these devices always suffer from complex multi-gate electrode structure, and hence face challenges in complicated inter-connection design and excessive voltage source requirement for circuit implementation. Here, we develop a three-terminal CMOSFET using ambipolar 2D material based on the drain electric field-induced carrier injection self-blocking mechanism. The designed drain electrode can effectively suppress carrier injection from the drain to the channel material, while the gate voltage can only regulate carrier injection in the source region. As a result, we can configure the device as either N-field-effect transistors (FET) or P-FET with a high current on/off ratio of over 105 by adjusting the three voltages (gate, source, and drain). Furthermore, we utilize these devices to demonstrate multifunctional wave modulator, low-static-power logic inverter (<5 pW), and combinational logic computing in the form of a compact complementary circuit. Our work would explore an efficient approach for implementing complementary circuits using 2D materials. [ABSTRACT FROM AUTHOR]

We report the nonvolatile modulation of microwave conductivity in ferroelectric PbZr0.2Ti0.8O3-gated ultrathin LaNiO3/La0.67Sr0.33MnO3 correlated oxide channel visualized by microwave impedance microscopy. Polarization switching is obtained by applying a tip bias above the coercive voltage of the ferroelectric layer. The microwave conductivity of the correlated channel underneath the up- and down-polarized domains has been quantified by finite-element analysis of the tip-sample admittance. At room temperature, a resistance on/off ratio above 100 between the two polarization states is sustained at frequencies up to 1 GHz, which starts to drop at higher frequencies. The frequence-dependence suggests that the conductance modulation originates from ferroelectric field-effect control of carrier density. The modulation is nonvolatile, remaining stable after 6 months of domain writing. Our work is significant for potential applications of oxide-based ferroelectric field-effect transistors in high-frequency nanoelectronics and spintronics. [ABSTRACT FROM AUTHOR]

[Display omitted] Two-dimensional noble transition metal chalcogenide (NTMC) semiconductors represent compelling building blocks for fabricating flexible electronic and optoelectronic devices. While binary and ternary compounds have been reported, the existence of quaternary NTMCs with a greater elemental degree of freedom remains largely unexplored. This study presents the pioneering experimental realization of a novel semiconducting quaternary NTMC material, AuPdNaS 2 , synthesized directly on Au foils through chemical vapor deposition. The ribbon-shaped morphology of the AuPdNaS 2 crystal can be finely tuned to a thickness as low as 9.2 nm. Scanning transmission electron microscopy reveals the atomic arrangement, showcasing robust anisotropic features; thus, AuPdNaS 2 exhibits distinct anisotropic phonon vibrations and electrical properties. The field-effect transistor constructed from AuPdNaS 2 crystal demonstrates a pronounced anisotropic conductance (σ max / σ min = 3.20) under gate voltage control. This investigation significantly expands the repertoire of NTMC materials and underscores the potential applications of AuPdNaS 2 in nano-electronic devices. [ABSTRACT FROM AUTHOR]

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16nm MOS-GNRFET model. [ABSTRACT FROM AUTHOR]

Information industry is one of the major drivers of the world economy. Its rapid growth, however, leads to severe heat problem which strongly hinders further development. This calls for a non-charge-based technology. Magnon, capable of transmitting spin information without electron movement, holds tremendous potential in post-Moore era. Given the cornerstone role of the field effect transistor in modern electronics, creating its magnonic equivalent is highly desired but remains a challenge. Here, we demonstrate a nonvolatile three-terminal lateral magnon field effect transistor operating at room temperature. The device consists of a ferrimagnetic insulator (Y3Fe5O12) deposited on a ferroelectric material [Pb(Mg1/3Nb2/3)0.7Ti0.3O3 or Pb(Zr0.52Ti0.48)O3], with three Pt stripes patterned on Y3Fe5O12 as the injector, gate, and detector, respectively. The magnon transport in Y3Fe5O12 can be regulated by the gate voltage pulses in a nonvolatile manner with a high on/off ratio. Our findings provide a solid foundation for designing energy-efficient magnon-based devices. Searching non-charge-based devices is crucial for sustainable information processing. Here, the authors make a nonvolatile magnon field effect transistor at room temperature, enabling efficient magnon transport control via the gate voltage pulses. [ABSTRACT FROM AUTHOR]

Van der Waals integration of freestanding perovskite-oxide membranes with two-dimensional semiconductors has emerged as a promising strategy for developing high-performance electronics, such as field-effect transistors. In these innovative field-effect transistors, the oxide membranes have primarily functioned as dielectric layers, yet their great potential for structural tunability remains largely untapped. Free of epitaxial constraints by the substrate, these freestanding membranes exhibit remarkable structural tunability, providing a unique material system to achieve huge strain gradients and pronounced flexoelectric effects. Here, by harnessing the excellent structural tunability of PbTiO3 membranes and modulating the underlying substrate's elasticity, we demonstrate the tip-pressure-induced polarization switching with an ultralow pressure (down to 0.06 GPa). Moreover, as an application demonstration, we develop a prototype non-volatile ferroelectric field-effect transistor integrated on silicon that can be operated mechanically and electrically. Our findings underscore the great potential of oxide membranes for utilization in advanced non-volatile electronics and highly sensitive pressure sensors. The authors realize low-pressure-driven polarization switching in PbTiO3 membranes by leveraging their structural tunability and substrate elasticity, enabling ferroelectric field-effect transistors on silicon, operatable mechanically and electrically. [ABSTRACT FROM AUTHOR]

Three different metal stacks, namely Ti/Au, Ni/Au and Sc/Au, were examined as Ohmic metal contacts to Si-doped, n-type (4.1 × 1019 cm−3), 300-nm thick (Al0.18Ga0.82)2O3 layers grown by metal-organic chemical vapor deposition. This is a typical composition used for (AlxGa1-x)2O3 /Ga2O3 heterostructure field effect transistors. The effects of postdepositional annealing (300–475 °C) were examined through circular transfer length method (CTLM) measurements to determine both the transfer resistance and specific contact resistivity. The lowest resistances were achieved with Ti/Au, with specific contact resistivity 1.2 × 10–4 Ω·cm2 and transfer resistance 3.82 Ω·mm for as-deposited contacts. Annealing was found to degrade both of these resistances in all cases from the as-deposited values, even though the AGO sheet resistance decreased slightly, from 1191 Ω/□ to 905 Ω/□ after annealing at 475 °C. The temperature dependence of specific contact resistivity is also investigated. [ABSTRACT FROM AUTHOR]

Despite recent dramatic improvements in the electronic characteristics of stretchable organic field-effect transistors (FETs), their low operational stability remains a bottleneck for their use in practical applications. Here, the operational stability, especially the bias-stress stability, of semiconducting polymer-based FETs under various tensile strains is investigated. Analyses on the structure of stretched semiconducting polymer films and spectroscopic quantification of trapped charges within them reveal the major cause of the strain-dependent bias-stress instability of the FETs. Devices with larger strains exhibit lower stability than those with smaller strains because of the increased water content, which is accompanied by the formation of cracks and nanoscale cavities in the semiconducting polymer film as results of the applied strain. The strain-dependence of bias-stress stability of stretchable OFETs can be eliminated by passivating the devices to avoid penetration of water molecules. This work provides new insights for the development of bias-stable stretchable OFETs. [ABSTRACT FROM AUTHOR]

The observation of the gate-controlled supercurrent (GCS) effect in superconducting nanostructures increased the hopes for realizing a superconducting equivalent of semiconductor field-effect transistors. However, recent works attribute this effect to various leakage-based scenarios, giving rise to a debate on its origin. A proper understanding of the microscopic process underlying the GCS effect and the relevant time scales would be beneficial to evaluate the possible applications. In this work, we observed gate-induced two-level fluctuations between the superconducting state and normal state in Al/InAs nanowires (NWs). Noise correlation measurements show a strong correlation with leakage current fluctuations. The time-domain measurements show that these fluctuations have Poissonian statistics. Our detailed analysis of the leakage current measurements reveals that it is consistent with the stress-induced leakage current (SILC), in which inelastic tunneling with phonon generation is the predominant transport mechanism. Our findings shed light on the microscopic origin of the GCS effect and give deeper insight into the switching dynamics of the superconducting NW under the influence of the strong gate voltage. It was recently shown that a voltage could be used to control a supercurrent in superconducting nanostructures, much like a transistor, however, the exact origin of this effect has been debated. Here Elalaily et al. show via noise measurements that the suppression of the supercurrent in the superconducting device arises due to excitation emission by inelastic tunneling of the electrons through the trap states created by stressing the oxide layer between the gate and the NW under a high electric field. [ABSTRACT FROM AUTHOR]

Three different metal stacks, namely Ti/Au, Ni/Au and Sc/Au, were examined as Ohmic metal contacts to Si-doped, n-type (4.1 × 1019 cm−3), 300-nm thick (Al0.18Ga0.82)2O3 layers grown by metal-organic chemical vapor deposition. This is a typical composition used for (AlxGa1-x)2O3 /Ga2O3 heterostructure field effect transistors. The effects of postdepositional annealing (300–475 °C) were examined through circular transfer length method (CTLM) measurements to determine both the transfer resistance and specific contact resistivity. The lowest resistances were achieved with Ti/Au, with specific contact resistivity 1.2 × 10–4 Ω·cm2 and transfer resistance 3.82 Ω·mm for as-deposited contacts. Annealing was found to degrade both of these resistances in all cases from the as-deposited values, even though the AGO sheet resistance decreased slightly, from 1191 Ω/□ to 905 Ω/□ after annealing at 475 °C. The temperature dependence of specific contact resistivity is also investigated. [ABSTRACT FROM AUTHOR]

Impact ionization effect has been demonstrated in transistors to enable sub-60 mV dec−1 subthreshold swing. However, traditionally, impact ionization in silicon devices requires a high operation voltage due to limited electrical field near the device drain, contradicting the low energy operation purpose. Here, we report a vertical subthreshold swing device composed of a graphene/silicon heterojunction drain and a silicon channel. This structure creates a low voltage avalanche impact ionization phenomenon and leads to steep switching of the silicon-based device. Experimental measurements reveal a small average subthreshold swing of 16 µV dec−1 over 6 decades of drain current and nearly hysteresis-free, and the operating voltage at which a vertical subthreshold swing occurs can be as low as 0.4 V at room temperature. Furthermore, a complementary silicon-based logic inverter is experimentally demonstrated to reach a voltage gain of 311 at a supply voltage of 2 V. Yuan et al. report a nearly vertical subthreshold swing field-effect transistor consists of a graphene/silicon heterojunction drain and a silicon channel. The device enables nearly hysteresis-free transistors with subthreshold swing of 16 µV dec−1, and a complementary logic inverter with gain of 311. [ABSTRACT FROM AUTHOR]

Feedback field-effect transistors (FBFETs) have been studied to obtain near-zero subthreshold swings at 300 K with a high on/off current ratio ~1010. However, their structural complexity, such as an epitaxy process after an etch process for a Si channel with a thickness of several nanometers, has limited broader research. We demonstrated a FBFET using in-plane WSe2 p−n homojunction. The WSe2 FBFET exhibited a minimum subthreshold swing of 153 mV/dec with 30 nm gate dielectric. Our modeling-based projection indicates that the swing of this device can be reduced to 14 mV/dec with 1 nm EOT. Also, the gain of the inverter using the WSe2 FBFET can be improved by up to 1.53 times compared to a silicon CMOS inverter, and power consumption can be reduced by up to 11.9%. [ABSTRACT FROM AUTHOR]

As one of the most promising electronic devices in the post-Moore era, nanoscale vacuum field emission transistors (VFETs) have garnered significant attention due to their unique electron transport mechanism featuring ballistic transport within vacuum channels. Existing research on these nanoscale vacuum channel devices has primarily focused on structural design for logic circuits. Studies exploring their application potential in other vital fields, such as sensors based on VFET, are more limited. In this study, for the first time, the design of a vacuum field emission transistor (VFET) coupled with a piezoelectric microelectromechanical (MEMS) sensing unit is proposed as the artificial mechanoreceptor for sensing purposes. With a negative threshold voltage similar to an N-channel depletion-mode metal oxide silicon field effect transistor, the proposed VFET has its continuous current tuned by the piezoelectric potential generated by the sensing unit, amplifying the magnitude of signals resulting from electromechanical coupling. Simulations have been conducted to validate the feasibility of such a configuration. As indictable from the simulation results, the proposed piezoelectric VFET exhibits high sensitivity and an electrically adjustable measurement range. Compared to the traditional combination of piezoelectric MEMS sensors and solid-state field effect transistors (FETs), the piezoelectric VFET design has a significantly reduced power consumption thanks to its continuous current that is orders of magnitude smaller. These findings reveal the immense potential of piezoelectric VFET in sensing applications, building up the basis for using VFETs for simple, effective, and low-power pre-amplification of piezoelectric MEMS sensors and broadening the application scope of VFET in general. [ABSTRACT FROM AUTHOR]

In this paper, we propose an ultrascaled WS2 field-effect transistor equipped with a Pd/Pt sensitive gate for high-performance and low-power hydrogen gas sensing applications. The proposed nanosensor is simulated by self-consistently solving a quantum transport equation with electrostatics at the ballistic limit. The gas sensing principle is based on the gas-induced change in the metal gate work function. The hydrogen gas nanosensor leverages the high sensitivity of two-dimensional WS2 to its sur-rounding electrostatic environment. The computational investigation encompasses the nanosensor's behavior in terms of potential profile, charge density, current spectrum, local density of states (LDOS), transfer characteristics, and sensitivity. Additionally, the downscaling-sensitivity trade-off is analyzed by considering the impact of drain-to-source voltage and the electrostatics parameters on subthreshold performance. The simulation results indicate that the downscaling-sensitivity trade-off can be optimized through enhancements in electrostatics, such as utilizing high-k dielectrics and reducing oxide thickness, as well as applying a low drain-to-source voltage, which also contributes to improved energy efficiency. The proposed nanodevice meets the prerequisites for cutting-edge gas nanosensors, offering high sensing performance, improved scaling capability, low power consumption, and complementary metal–oxide–semiconductor compatibility, making it a compelling candidate for the next generation of ultrascaled FET-based gas nanosensors. [ABSTRACT FROM AUTHOR]

Thermal management becomes increasingly important in silicon gate‐all‐around (GAA) field‐effect transistor (FETs) for 3 nm technology node and beyond. The channel thermal conductivity significantly differs from bulk silicon. Precise determination of thermal conductivity is crucial for device evaluation and optimization. This study investigates the thermal conductivity of silicon nanowires, examining the complex interplay between size and channel orientation. The conventional nonequilibrium molecular dynamics (NEMD) method is used with the standard Stillinger–Weber potential at the atomic scale. The results indicate that the thermal conductivity of silicon nanowires along the [100] direction increases monotonically with both length (L) and cross‐sectional side length (D). Conversely, the [110] direction exhibits nonmonotonic variation in thermal conductivity with D, due to increased acoustic–optic phonon scattering. For GAA FET devices with a silicon nanowire channel of L = 20 nm and D = 5 nm, the NEMD calculations yield thermal conductivities of 10.8 W m·K−1 for the [100] direction and 25.3 W m·K−1 for the [110] direction. Subsequently, the self‐heating effect (SHE) in silicon nanowire GAA FETs by technology computer‐aided design with the modified channel conductivity is analyzed. The results suggest that silicon nanowires with the [110] transport direction are more suitable for device design. [ABSTRACT FROM AUTHOR]

A quasi‐vertical gallium nitride (GaN) fin field effect transistor (FinFET) is designed and analyzed to assess the performance of electrical parameters. The device is deployed on a silicon carbide (SiC) substrate and analyzed using technology computer‐aided design (TCAD). The donor concentration in the critical regions is identified as a significant limiting factor for FinFET electrical properties. Hence, the influence of channel and drift layer doping concentrations (Nd) on performance characteristics is investigated in this work. The electrical characteristics such as threshold voltage, ION/IOFF ratio, subthreshold swing (SS), specific ON‐resistance, and breakdown voltage (VBV) are evaluated for various doping profiles. The doping profile with channel and drift layer concentration of 4 × 1015 cm−3 for a 300 nm fin width and 1 μm thick drift layer exhibits normally OFF behavior with a threshold voltage (Vt) of 1.5 V. It also demonstrates a VBV of 139 V. The corresponding doping profile reveals a low SS of 61 mV dec−1, which is comparable to other similar power devices. This demonstrates the significant potential of the device for medium‐power switching applications. [ABSTRACT FROM AUTHOR]

Field effect transistors based on 2D layered material have gained significant potential in emerging technologies, such as neuromorphic computing and ultrafast memory response for artificial intelligence applications. This study proposes a facile approach to fabricate an optoelectronic artificial synapse for neuromorphic computing and light‐decoding information system by utilizing the 2D heterostructure of CrSBr/PtS2 to overcome circuit complexity. The CrSBr layer serves as a trapping layer, while PtS2, mounted on top of CrSBr, acts as a channel layer. PtS2 exhibits n‐type semiconductor behavior with a hysteresis that varies with the thickness of the underlying CrSBr layer. The heterostructure device, featuring a 96.3 nm thick CrSBr layer, exhibited a large memory window of 11.9 V when the gate voltage is swept from −10 V to +10 V. Various synaptic behaviors are effectively demonstrated, including paired‐pulse facilitation, excitatory postsynaptic current, optical spike number and intensity‐dependent plasticity using laser light at a wavelength of 365 nm. The device achieves 26 distinct output signals depending on the intensity of the incident laser light, ranging from 10 to 385 mW cm−2, enabling its applications for light‐decoded information security systems. Thus, the investigation presents a unique approach to artificial intelligence and cybersecurity systems. [ABSTRACT FROM AUTHOR]

In food safety analysis, the detection and control of foodborne pathogens and their toxins are of great importance. Monitoring of virus transmission is equally important, especially in light of recent findings that coronaviruses have been detected in frozen foods and packages during the current global epidemic of coronavirus disease 2019. In recent years, field-effect transistor (FET) biosensors have attracted considerable scholarly attention for pathogenic microorganisms and toxins detection and sensing due to their rapid response time, high sensitivity, wide dynamic range, high specificity, label-free detection, portability, and cost-effectiveness. FET-based biosensors can be modified with specific recognition elements, thus providing real-time qualitative and semiquantitative analysis. Furthermore, with advances in nanotechnology and device design, various high-performance nanomaterials are gradually applied in the detection of FET-based biosensors. In this article, we review specific detection in different biological recognition elements are immobilized on FET biosensors for the detection of pathogenic microorganisms and toxins, and we also discuss nonspecific detection by FET biosensors. In addition, there are still unresolved challenges in the development and application of FET biosensors for achieving efficient, multiplexed, in situ detection of pathogenic microorganisms and toxins. Therefore, directions for future FET biosensor research and applications are discussed. [ABSTRACT FROM AUTHOR]

For the past few decades, metal–oxide–semiconductor field-effect transistors (MOSFETs) have been the most important application in IC circuits. In certain circuit applications, the breakdown voltage and specific on-resistance serve as key electrical parameters. This article introduces a readily accessible approach to enhance the source–drain breakdown voltage (BVDS) of MOSFETs based on the Bipolar-CMOS-DMOS (BCD) platform without extra costs. By attentively refining the process steps and intricacies of the doping procedures, the breakdown voltages of NMOS and PMOS experienced increments of 3.4 V and 4.6 V, translating to enhancements of 31.5% and 50.3%. Parallel simulations offer insightful mechanistic explanations through simulation tools, facilitating superior outcomes. This initiative lays significant groundwork for the advancement of a comprehensive BCD process development framework. [ABSTRACT FROM AUTHOR]

The multifunctionality feature of graphene field-effect transistors (GFETs) is exploited here to design circuit building blocks of high-data-rate modulators by using a physics-based compact model. Educated device performance projections are obtained with the experimentally calibrated model and used to choose an appropriate improved feasible GFET for these applications. Phase-shift and frequency-shift keying (PSK and FSK) modulation schemes are obtained with 0.6   G Hz GFET-based multifunctional circuits used alternatively in different operation modes: inverting and in-phase amplification and frequency multiplication. An adequate baseband signal applied to the transistors' input also serves to enhance the device and circuit performance reproducibility since the impact of traps is diminished. Quadrature PSK is also achieved by combining two GFET-based multifunctional circuits. This device circuit co-design proposal intends to boost the heterogeneous implementation of graphene devices with incumbent technologies into a single chip: the baseband pulses can be generated with CMOS technology as a front end of line and the multifunctional GFET-based circuits as a back end of line. [ABSTRACT FROM AUTHOR]

The pulse laser emission circuit plays a crucial role as the emission unit of time-of-flight (TOF) LiDAR. This paper proposes a nanosecond-level pulse laser diode array drive circuit for LiDAR, primarily aimed at addressing the issue of high-speed scanning drive for the laser diode array at the emission end of solid-state LiDAR. Based on the single pulse laser diode drive circuit, this paper innovatively designs a circuit that includes modules such as a boost circuit, linear power supply, high-speed gate driver, GaN field-effect transistor, and pulse narrowing circuit, realizing an 8-channel laser diode array drive circuit. This circuit can achieve a pulse laser array drive with a single channel operating frequency of greater than 100 kHz, an output pulse width of less than 5 ns, a peak power greater than 75 W, and a channel switching time that does not exceed 1 μs. A field programmable gate array (FPGA) is used to control the operation of this circuit and perform a series of performance tests. Experimental results show that this circuit has a high repetition rate, large output power, a narrow pulse width, and fast switching speeds, making it highly suitable for use in the optical emission module of solid-state LiDAR. [ABSTRACT FROM AUTHOR]

FinFET transistors with fin channel lengths of 160 nm and 2000 nm and a planar MOSFET transistor with channel lengths of 180 nm and 90 nm are presented with characteristic curves at various Gate biases. A finalized algorithm with kink effects was effectively responsible for addressing the field effect transistors. The algorithm included the modified conventional current–voltage formula and a nonlinear heat-associated kink solution which was simplified as a Gaussian form. Three parameters in the modified model included kN (which was related with channel width, channel length, and gate oxide capacitor, and was proportional to the mobility of carriers), Vth (threshold voltage), and λ (the inverse of early voltage). Those parameters were determined to minimize the discrepancies between the measured data and the fitting values, but left kinks located at around (VGS-Vth), which were deliberately eliminated by the Gaussian form because of the agitation of thermal kink effects. The whole fitting was made to be as close as possible to the as-measured IDS-VDS. In the meantime, those determined parameters were physically meaningful after the analysis had been performed. [ABSTRACT FROM AUTHOR]

This article explores the progress and challenges of the graphene industry 20 years after its discovery. Graphene, a thin sheet of carbon, was initially praised for its unique properties but faced difficulties in mass production. However, companies are now finding success by exploring different forms of graphene and improving production methods. The article highlights the Graphene Engineering Innovation Centre in Manchester, which supports companies working with graphene. It also discusses the various applications of graphene in fields such as electronics, coatings, and medical devices. Despite challenges, there is optimism about graphene's future impact and the emergence of other 2D materials. [Extracted from the article]

The excellent complementary metal-oxide-semiconductor compatibility and rich physicochemical properties of hafnia-based materials, in particular the unique ferroelectricity that surpasses of conventional ferroelectrics, make hafnia-based devices promising candidates for industrial applications. This Perspective examines the fundamental properties of hafnia-based materials relevant to neuromorphic devices, including their dielectric, ferroelectric, antiferroelectric properties, and the associated ultra-high oxygen-ion conductivity. It also reviews neuromorphic devices developed leveraging these properties, such as resistive random-access memories, ferroelectric random-access memories, ferroelectric tunnel junctions, and (anti)ferroelectric field-effect transistors. We also discuss the potential of these devices for mimicking synaptic and neuronal functions and address the challenges and future research directions. Hafnia-based neuromorphic devices promise breakthrough performance improvements through material optimization, such as crystallization engineering and innovative device configuration designs, paving the way for advanced artificial intelligence systems. [ABSTRACT FROM AUTHOR]

In recent years, silicon‐based room temperature Terahertz (THz) detectors have become the most optimistic research area because of their high speed, low cost, and unimpeded compatibility with mainstream complementary metal‐oxide‐semiconductor (CMOS) device technologies. However, Silicon (Si) suffers from low responsivity and high noise at THz frequencies. In this review, the recent advances in Si‐based THz detectors using silicon‐on‐insulator (SOI) substrates are presented. These offer several advantages over bulk counterparts, such as reduced parasitic capacitance, enhanced electric field confinement, and improved thermal isolation. The different types of THz detectors exploiting SOI substrate, such as conventional metal‐oxide‐semiconductor field effect transistors (MOSFETs), junction‐less MOSFETs, junction‐less nanowires field effect transistors (JLNWFETs), micro‐electromechanical system (MEMS), metal‐semiconductor‐metal (MSM) structures, and single electron transistor (SET), are discussed, and their key performances in terms of responsivity, noise equivalent power (NEP), bandwidth, and dynamic range are compared. The challenges and opportunities for further improvement of SOI THz detectors, such as device scaling, integration, and modulation, are also highlighted. This review may offer compelling evidence supporting the idea that SOI THz detectors have the potential to facilitate high performance, low power consumption, and scalability—qualities essential for advancing next‐level technologies. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) multiferroic materials are recognized as promising candidates for next-generation nanodevices due to their tunable magnetoelectric coupling and distinctive physical phenomena. In this study, we proposed a novel 2D multiferroic van der Waals heterostructure (vdWH) by stacking atomic layers of ferroelectric In2Se3 and ferromagnetic MnI3. Using first-principles calculations, we found that the MnI3/In2Se3 vdWH exhibit robust metallic conductivity across various spin and polarization states, preserving the distinctive band characteristics of isolated In2Se3 and MnI3. However, the alignment of Fermi levels causes the conduction band minimum (CBM) and valence band maximum (VBM) of In2Se3 and MnI3 to shift relative to their original band structures. Remarkably, the MnI3/In2Se3 with the upward polarization state of In2Se3 exhibits an Ohmic contact. Switching the polarization direction of In2Se3 from upward to downward can transform the MnI3/In2Se3 vdWH from an Ohmic contact to a p-type Schottky contact, while also modifying its dipole moment, magnetic strength and direction. Based on these properties of MnI3/In2Se3 vdWH, we designed the field-effect transistors (FETs) with high on/off rates and nonvolatile data storage device. Furthermore, the Schottky barrier heights (SBHs), magnetic moment, and dipole moment of MnI3/In2Se3 vdWH can also be effectively regulated by reducing the interlayer distance. With the continuous reduction of the interlayer distance of MnI3/In2Se3 vdWH, its easy magnetization axis is expected to shift from in-plane to out-of-plane. These findings offer new insights for the design and development of the next-generation spintronic and nonvolatile memory nanodevices. [ABSTRACT FROM AUTHOR]