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The power requirements of wireless sensor networks and internet of things (IoT) applications heavily rely on batteries. It is crucial that the memory cells utilized in these applications must consume low-power to prolong the battery life. In this paper, a static-random access memory (SRAM) cell is introduced that incorporates eleven carbon nanotube field-effect transistors (CNTFETs). The proposed 11T CNTFET SRAM cell employs a single-ended approach for reading and writing data and read-decoupled approach to access data in the bit cell. In addition to this, Schmitt-trigger (ST) inverter is incorporated within the bit cell, to enhance its stability and power efficiency. To evaluate the performance of the proposed 11T CNTFET SRAM cell, 32 nm CNTFET model developed by the Stanford University- and HSPICE simulation tool are used for the simulations. The proposed 11T CNTFET bit cell's results show write power, hold power, read power, write static noise margin, hold static noise margin read static noise margin, write delay and read delay of 0.182 nW, 0.2 nW, 0.197 nW, 453.5 mV, 380.5 mV, 383.3 mV, 102 pS and 41.9 pS, respectively at VDD = 0.9 V. Comprehensive parametric simulations are also carried out to analyze the impact of various CNTFET parameters on performance metrics of proposed SRAM cell. The performance of proposed SRAM is fairly compared with existing SRAM cells implemented with CNTFETs and results are found to be quite encouraging. The proposed SRAM cell finds its suitability for use in designing memory devices targeted for wireless sensor networks, Internet of Things and smart biomedical gadgets. [ABSTRACT FROM AUTHOR]

As memories dominate the system-on-chip (SoC), their quality significantly impacts the chip manufacturing yield. There is a growing need to reduce the chip production time and cost, which mainly depends on the testing phase. Hence, a memory built-in self-test (MBIST) utilizing a low-complexity, high-fault-coverage test algorithm is essential for efficient and thorough memory testing. The March AZ1 algorithm, with 13N complexity, was created earlier to balance the test length and fault coverage. However, poor positioning of a write operation in its test sequence caused the reduction of the transition coupling fault (CFtr) detection. This paper presents the creation of the March AZ algorithm, modified from the March AZ1 algorithm, to increase CFtr coverage while preserving the same complexity. It was accomplished by analyzing the fault coverage offered by the March AZ1 algorithm and then reorganizing its test sequence to address the limitation in detecting CFtr. The newly produced March AZ1 algorithm was successfully implemented in an MBIST controller. The simulation tests validated its functionality and demonstrated that the CFtr coverage was enhanced from 62.5% to 75%, achieving an overall fault coverage of 83.3%. Therefore, with 13N complexity, it offers the best fault coverage among all the existing test algorithms with a complexity below 18N. [ABSTRACT FROM AUTHOR]

The 8T static random-access memory (SRAM) cell using carbon nanotube technology, positive feedback, and dynamic supply voltage scaling are presented in this work. Positive feedback strengthens the feedback loop and enhances the noise margin making SRAM cells less susceptible to disturbance and improving the stabilization of the cell by improving read and write timing response. Positive feedback control (PFC) adjusts the cell's operating condition based on its current and external condition under varying conditions. The positive power supply controlled (PPC) technique in SRAM cell design improves the stability and leakage power consumption by adjusting the voltage level during the operation mode of the cell. The experiment with carbon nanotube field-effect transistor (CNTFET) offers higher drive current and lower power consumption compared to conventional silicon-based transistors. The performance of the 8T SRAM cell incorporating PFC and PPC transistor is investigated with Synopsys HSPICE using the Stanford CNFET model. The proposed SRAM cell architecture archives a 99.99% improvement in power consumption and delay product (PDP) compared to a conventional 6T SRAM cell. The static noise margin of 300 mV ensures better noise immunity and reliable retention of data. The mean value of power consumption is 43.19 nW showing a variance of 93.16 fW and a standard deviation (σ) of 305.2 nW and the mean value of delay is 14.71 ps showing a variance of 1.010 and a standard deviation (σ) of 10.05 ps. CNTFET 8T SRAM cell with the combination of positive feedback and dynamic feedback enhances the performance and efficiency of the memory cell under varying conditions. [ABSTRACT FROM AUTHOR]

As CMOS technology has advanced, the transistor integration density of static random-access memory (SRAM) cells has increased. This has led to a reduction in the critical charge of sensitive nodes, making the SRAM cells more susceptible to soft errors. When high-energy particles in space strike the sensitive nodes of an SRAM cell, a single-event upset (SEU) can occur, altering the stored data. Additionally, the charge-sharing effect between transistors can cause single-event multi-node upsets (SEMNUs). To address these challenges, this paper proposes a radiation-hardened 16T SRAM cell optimized for stability and power, referred to as RHSP16T. The performance of the proposed RHSP16T cell was compared with other radiation-hardened SRAM cells, including QUC-CE12T, WE-QUATRO, RHBD10T, RHD12T, and RSP14T. Simulation results indicate that the proposed RHSP16T cell exhibits higher read and write stability, along with lower-leakage power consumption. compared with all other cells. This demonstrates that RHSP16T ensures high reliability for stored data. Furthermore, EQM results show that the RHSP16T cell outperformed the compared designs in overall SRAM cell performance. The proposed integrated circuit was implemented in a 90 nm CMOS process and operated on 1 V supply voltage. [ABSTRACT FROM AUTHOR]

The seamless handover of mobile devices is critical for maximizing the potential of smart city applications, which demand uninterrupted connectivity, ultra-low latency, and performance in diverse environments. Fifth-generation (5G) and beyond-5G networks offer advancements in massive connectivity and ultra-low latency by leveraging advanced technologies like millimeter wave, massive machine-type communication, non-orthogonal multiple access, and beam forming. However, challenges persist in ensuring smooth handovers in dense deployments, especially in higher frequency bands and with increased user mobility. This paper presents an adaptive handover management scheme that utilizes reinforcement learning to optimize handover decisions in dynamic environments. The system selects the best target cell from the available neighbor cell list by predicting key performance indicators, such as reference signal received power and the signal–interference–noise ratio, while considering the fixed time-to-trigger and hysteresis margin values. It dynamically adjusts handover thresholds by incorporating an offset based on real-time network conditions and user mobility patterns. This adaptive approach minimizes handover failures and the ping-pong effect. Compared to the baseline LIM2 model, the proposed system demonstrates a 15% improvement in handover success rate, a 3% improvement in user throughput, and an approximately 6 sec reduction in the latency at 200 km/h speed in high-mobility scenarios. [ABSTRACT FROM AUTHOR]

High-energy particles found in space environment can cause single event upsets (SEUs). The severe environments found in space are too harsh for conventional 6T static random-access memory (SRAM) cell as its data get altered when a radiation particle strikes a susceptible place of the cell. Therefore, creating an SRAM that can withstand these demanding space circumstances is essential. This paper proposes a High Speed Radiation Hardened 12T (HSRH12T) SRAM cell which is suitable for low power applications and mitigates the effect of both SEU and multi-bit soft errors. All of the HSRH12T sensitive nodes are capable of recovering their data, even in the event that a radiation impact flips the node values. The HSRH12T demonstrates up to 1.6 × /7.88 × /1.31 × /23.37 × reduction in read delay (T R A), write delay (T W A), leakage and dynamic power consumption, respectively. The proposed cell exhibits up to 1.64 × greater critical charge compared to the other considered cells. [Display omitted] • Its higher critical charge at sensitive nodes ensure strong SEU/SEMNU tolerance. • Utilization of more PMOS transistors reduces sensitive nodes, and SEU impact. • Stacked transistors in the latch core effectively reduce leakage power. • It's dynamic power is less due to the lower bitline capacitance. [ABSTRACT FROM AUTHOR]

This paper proposes a hybrid MOSFET-TFET 11T (HMT-11T) SRAM cell, which circumvents the forward p i-n current of TFET devices and diminishes its read/write delay by employing a hybrid structure to enhance its read/write current. Furthermore, the HMT-11T SRAM cell not only effectively avoids the half-selected disturbance, but also reduces the cell area by combining the read path with the access transistor. When VDD = 0.7 V, the static power consumption of the HMT-11T SRAM cell is about four orders of magnitude lower than that of the 12T (ST-12T) SRAM cell consisting of a schmitt-trigger structure; the dynamic power consumption is 75.31% lower than that of the ST-12T SRAM cell. At VDD = 0.7 V, the read delay of the HMT-11T SRAM cell is respectively 65.47% and 65.42% lower than that of the ST-12T and combinational 12T (CA-12T) SRAM cells; the write delay is respectively 28.09% and 70.87% lower than that of the ST-12T and the CA-12T SRAM cell. [ABSTRACT FROM AUTHOR]

This work presents two innovative 12T cells combining tunnel field-effect transistor (TFET) and fin field-effect transistor (FinFET) technologies. These cells address reverse bias current issues by incorporating separate paths for reading data and write enhancement cut transistors, enhancing hold/read/write static noise margin (H/R/WSNM), reducing read time, and minimizing power consumption from TFET leakage. At 0.6 V, the first (second) SRAM cell shows a WSNM improvement over O_7T, 8T, CA_10T, 12T, and HF_10T cells by 152 % (93 %), 152 % (93 %), 157.7 % (97.5 %), 95 % (50 %), and 104 % (57 %), respectively. The leakage power of the first (second) 12T TFET SRAM cell is two (four) orders of magnitude lower than O_7T and 8T SRAM cells. These hybrid SRAM cells also exhibit faster read operations across V DD voltage levels (0.3 V–1 V) and the first 12T cell demonstrates shorter write access times than 12T and CA_10T SRAM cells. These characteristics make the proposed cells particularly suitable for energy-efficient IoT devices and medical applications, where balancing power, area, performance, and data integrity is critical. • Two innovative 12T SRAM cells using TFET and FinFET technologies for greater performance. • Significant improvement in Write Static Noise Margin (WSNM) compared to existing SRAM cells. • Achieves two to four orders of magnitude lower leakage power than conventional SRAM cells. • Faster read operations and reduced write access times across varying V DD supply voltage levels. [ABSTRACT FROM AUTHOR]

The Complementary FET (CFET) architecture offers a more promising solution for achieving higher transistor density in sub-3 nm technology nodes. In this study, we use 3D TCAD simulations to conduct Monte Carlo based single-particle incidence analysis on FinFET and four types of CFET 6-Transistor (6T) Static Random Access Memory (SRAM). We identify the linear energy transfer (LET) thresholds for the five SRAM structures and analyze the causes of Single Event Upset (SEU) in three sensitive areas. Simulation results indicate that the SEU LET threshold of the CFET SRAM in the Fin-On-GAA-Fin (FOGF) structure is higher than that of the Fin-On-Trapezoidal-Fin (FOTF) structure. This is because both the upper and lower layers of the CFET SRAM in the FOGF structure use the GAA structure to isolate from the substrate, making it more difficult to trigger the bipolar amplification effect. The CFET SRAM using the Staggered FOGF structure demonstrates the best radiation resistance when the LET is below 0.3 pC/μm, due to the more dispersed distribution of sensitive areas and the isolation of the lower PMOS from the substrate. We also calculate the SEU cross-sections of the five SRAMs under different LETs. Showing that CFET SRAM consistently exhibits better radiation resistance compared to FinFET SRAM. These findings suggest that advanced CFET technology could be effectively applied to the design of radiation-hardened SRAM. • Analyzed SEU mechanisms in CFET SRAM for reliability optimization • Proposed an innovative staggered CFET SRAM structure with enhanced radiation hardening • Sta-FOGF CFET SRAM structure has the highest SEU threshold and lowest SEU occurrence. • SEU-sensitive regions are concentrated near the channels and drains of PD and PG transistors. [ABSTRACT FROM AUTHOR]