1. Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture
- Author
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Cheng-Hsuan Li, Chia-Lin Yang, and Po-Han Wang
- Subjects
010302 applied physics ,Heterogeneous System Architecture ,Multi-core processor ,Hardware_MEMORYSTRUCTURES ,Computer science ,02 engineering and technology ,Parallel computing ,Cache pollution ,01 natural sciences ,020202 computer hardware & architecture ,Smart Cache ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Cache ,Latency (engineering) ,Multicore architecture ,Cache algorithms - Abstract
Shared last-level cache (LLC) management is a critical design issue for heterogeneous multi-cores. In this paper, we observe two major challenges: the contribution of LLC latency to overall performance varies among applications/cores and also across time; overlooking the off-chip latency factor often leads to adverse effects on overall performance. Hence, we propose a Latency Sensitivity-based Cache Partitioning (LSP) framework, including a lightweight runtime mechanism to quantify the latency-sensitivity and a new cost function to guide the LLC partitioning. Results show that LSP improves the overall throughput by 8% on average (27% at most), compared with the state-of-the-art partitioning mechanism, TAP.
- Published
- 2016
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