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The rapid proliferation of the Internet-of-Things (IoT) and the dramatic resurgence of artificial intelligence (AI) based application workloads has led to immense interest in performing inference on energy-constrained edge devices. Approximate computing (a design paradigm that yields large energy savings at the cost of a small degradation in application quality) is a promising technique to enable energy-efficient inference at the edge. This paper introduces the concept of an approximate inference system (AxIS) and proposes a systematic methodology to perform joint approximations across different subsystems in a deep neural network-based inference system, leading to significant energy benefits compared to approximating individual subsystems in isolation. We use a smart camera system that executes various convolutional neural network (CNN) based image recognition applications to illustrate how the sensor, memory, compute, and communication subsystems can all be approximated synergistically. We demonstrate our proposed methodology using two variants of a smart camera system: (a) Camedge, where the CNN executes locally on the edge device, and (b) Camcloud, where the edge device sends the captured image to a remote cloud server that executes the CNN. We have prototyped such an approximate inference system using an Altera Stratix IV GX-based Terasic TR4-230 FPGA development board. Experimental results obtained using six CNNs demonstrate significant energy savings (around 1.7× for Camedge and 3.5× for Camcloud) for minimal (

In this work, we propose dual mode ferroelectric transistors (D-FEFETs) that exhibit dynamic tuning of operation between volatile and non-volatile modes with the help of a control signal. We utilize the unique features of D-FEFET to design two variants of non-volatile flip-flops (NVFFs). In both designs, D-FEFETs are operated in the volatile mode for normal operations and in the non-volatile mode to backup the state of the flip-flop during a power outage. The first design comprises of a truly embedded non-volatile element (D-FEFET) which enables a fully automatic backup operation. In the second design, we introduce need-based backup, which lowers energy during normal operation at the cost of area with respect to the first design. Compared to a previously proposed FEFET based NVFF, the first design achieves 19% area reduction along with 96% lower backup energy and 9% lower restore energy, but at 14%-35% larger operation energy. The second design shows 11% lower area, 21% lower backup energy, 16% decrease in backup delay and similar operation energy but with a penalty of 17% and 19% in the restore energy and delay, respectively. System-level analysis of the proposed NVFFs in context of a state-of-the-art intermittently-powered system using real benchmarks yielded 5%-33% energy savings.

The intrinsic error resilience exhibited by emerging application domains enables a new dimension for energy optimization of computing systems, namely the introduction of a controlled amount of approximations during system operation in exchange for substantial energy savings. Prior work in the area of approximate computing has focused on individual subsystems of a computing system, e.g., the computational subsystem or the memory subsystem. Since they focus only on individual subsystems, these techniques are unable to exploit the large energy-saving opportunities that stem from adopting a full-system perspective and approximating multiple subsystems of a computing platform simultaneously in a coordinated manner. This paper proposes a systematic methodology to perform joint approximations across different subsystems, leading to significant energy benefits compared to approximating individual subsystems in isolation. We use the example of a smart camera system that executes various computer vision and image processing applications to illustrate how the sensing, memory, and processing subsystems can all be approximated synergistically. We have implemented such an approximate smart camera system using an Altera Stratix IV GX FPGA development board, a Terasic TRDBD5M 5 Megapixel camera module, and a 1GB DDR3 SODIMM module. Experimental results obtained using six application benchmarks demonstrate significant energy savings (around 7.5× on average) for minimal (< 1%) loss in application quality. Compared to approximating a single subsystem, the proposed full-system approximation methodology achieves additional energy benefits of 3.5× – 5.5× on average for minimal (< 1%) quality loss.

Physically Unclonable Functions (PUFs) have proved to be an effective and low-cost measure against counterfeiting by providing device authentication and secure key storage services. Memory based PUF implementations are an attractive option due to the ubiquitous nature of memory in electronic devices and the requirement of minimal (or no) additional circuitry. DRAM based PUFs are particularly advantageous due to their large address space and multiple controllable parameters during response generation. However, prior works on DRAM PUFs use a static response generation mechanism making them vulnerable to security attacks. Further, they result in very slow device authentication, are not applicable to off-the-shelf DRAM modules, or require DRAM power cycling prior to authentication. In this paper, we propose D-PUF, an intrinsically reconfigurable DRAM PUF based on refresh pausing. A key feature of the proposed DRAM PUF is that it can be reconfigured by varying the refresh-pause interval, which changes it's challenge-response behavior, making it robust against various attacks. We use the PUF to design a secure, low-overhead methodology for performing device authentication. The design is implemented and validated using an Altera Stratix IV GX FPGA based Terasic TR4-230 development board and several off-the-shelf 1GB DDR3 DRAM modules. Our experimental results demonstrate a 4.3×–6.4× reduction in authentication time, compared to previous work. Using controlled temperature and accelerated aging tests, we also demonstrate the robustness of our authentication mechanism to temperature variations and aging effects.

Advances in the physical sciences and engineering enable the development of internet-of-things (IoT) to understand, interface / interact and engineer physical world (systems). However, the deployment of multitude of wireless sensors and agents spanning many application domains (e.g., environmental, healthcare, smart interconnected vehicles and trucks, smart buildings) leads not only to tremendous requirements for communicating massive amounts of multiscale heterogeneous data, but also calls for developing efficient strategies for mathematical modeling of the sensed data while overcoming the energy wall. To address these outstanding challenges, out-of-the-box approaches need to be explored. In this tutorial paper, we discuss these outstanding problems and describe a few far-reaching design methodologies that achieve the most sought after features in autonomous IoT, viz. intelligent mining, smart trustworthy sensing, closed-loop (networked) control, and energy efficiency. Internet-of-things, autonomy, compact yet accurate models, network control, networks-on-chip, manycore.

The lack of post-deployment visibility into system behavior is one of the major challenges in ensuring the reliable operation of implantable medical devices (IMDs). While wireless connectivity is becoming common in IMDs for monitoring device status, conventional wireless links incur significant energy overheads for data acquisition, processing, and active radio transmission. While low-power transceivers have been introduced to reduce the energy consumed by the radio itself, the energy consumed by the microcontroller for processing data and controlling the radio has often been overlooked. As a result, in IMDs that have a stringent energy constraint, prolonged signal monitoring over a wireless channel is infeasible due to this prohibitively high power consumption.To address this challenge, we present TELEPROBE, which enables zero-power probing of signals in IMDs. TELEPROBE is a wireless, oscilloscope-like probing mechanism for IMDs that allows direct readout of analog/digital signals in real-time using an LC tank circuit, without any power overhead imposed on the IMD. We have designed and implemented fully functional prototypes of TeleProbe and demonstrated its utility in the context of two practical usage scenarios: in-situ power analysis and off-chip serial communication bus monitoring in IMDs.

Implantable and wearable medical devices are used for monitoring, diagnosis, and treatment of an ever-increasing range of medical conditions, leading to an improved quality of life for patients. The addition of wireless connectivity to medical devices has enabled post-deployment tuning of therapy and access to device data virtually anytime and anywhere but, at the same time, has led to the emergence of security attacks as a critical concern. While cryptography and secure communication protocols may be used to address most known attacks, the lack of a viable secure connection establishment and key exchange mechanism is a fundamental challenge that needs to be addressed. We propose a vibration-based secure side channel between an external device (medical programmer or smartphone) and a medical device. Vibration is an intrinsically short-range, user-perceptible channel that is suitable for realizing physically secure communication at low energy and size/weight overheads. We identify and address key challenges associated with the vibration channel, and propose a vibration-based wakeup and key exchange scheme, named SecureVibe, that is resistant to battery drain attacks. We analyze the risk of acoustic eavesdropping attacks and propose an acoustic masking countermeasure. We demonstrate and evaluate vibration-based wakeup and key exchange between a smartphone and a prototype medical device in the context of a realistic human body model.

In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in idle mode is often the bottleneck for battery lifetime. Existing solutions address this problem by placing the microcontroller in a low power (sleep) state when idle, and preserving application state either by retaining the data in-situ in SRAM, or by checkpointing it to Flash. However, both these approaches have notable drawbacks. In-situ data retention requires the SRAM to remain powered in sleep mode, while checkpointing to Flash involves significant energy and time overheads. This paper proposes a new ultra-low power sleep mode for microcontrollers that overcomes the limitations of both these approaches. Our technique, Hypnos, is based on the key observation that the on-chip SRAM in a microcontroller exhibits 100% data retention even at a much lower supply voltage (as much as 10x lower) than the typical operating voltage of the microcontroller. Hypnos exploits this observation by performing extreme voltage scaling when the microcontroller is in sleep mode. We implement and evaluate Hypnos for the TI MSP430G2452 microcontroller and show that the MCU draws only 26nA in the proposed sleep mode, which is 4x lower than any existing sleep mode that preserves SRAM contents. Further, we show that a complete wireless sensing system using Hypnos only depletes battery capacity by 42.6nAh in an hour. By decreasing the average power consumption to such minuscule levels, Hypnos takes a significant step forward in making perpetual systems a reality through the use of energy harvesting.

Various industry forecasts project that, by 2020, there will be around 50 billion devices connected to the Internet of Things (IoT), helping to engineer new solutions to societal-scale problems such as healthcare, energy conservation, transportation, etc. Most of these devices will be wireless due to the expense, inconvenience, or in some cases, the sheer infeasibility of wiring them. Further, many of them will have stringent size constraints. With no cord for power and limited space for a battery, powering these devices (to achieve several months to possibly years of unattended operation) becomes a daunting challenge. This paper highlights some promising directions for addressing this challenge, focusing on three main building blocks: (a) the design of ultra-low power hardware platforms that integrate computing, sensing, storage, and wireless connectivity in a tiny form factor, (b) the development of intelligent system-level power management techniques, and (c) the use of environmental energy harvesting to make IoT devices self-powered, thus decreasing -- in some cases, even eliminating -- their dependence on batteries. We discuss these building blocks in detail and illustrate case-studies of systems that use them judiciously, including the QUBE wireless embedded platform, which exploits the characteristics of emerging non-volatile memory technologies to seamlessly and efficiently enable long-running computations in systems that experience frequent power loss (i.e., intermittently powered systems).

The lack of post-deployment visibility into system operation is one of the major challenges in ensuring reliable operation of remotely deployed embedded systems such as wireless sensor nodes. Over the years, many software-based solutions (in the form of debugging tools and protocols) have been proposed for in-situ system monitoring. However, all of them share the trait that the monitoring functionality is implemented as software executing on the same embedded processor that the main application executes on. This is a poor design choice from a reliability perspective. This paper makes the case for a joint hardware-software solution to this problem and advocates the use of a dedicated reliability co-processor that is tasked with monitoring the operation of the embedded system. As an embodiment of this design principle, this paper presents Spi-Snooper, a co-processor augmented hardware platform specifically designed for network monitoring. Spi-Snooper is completely cross-compatible with the Telos wireless sensor nodes from an operational standpoint and is based on a novel hardware architecture that enables transparent snooping of the communication bus between the main processor and the radio of the wireless embedded system. The accompanying software architecture provides a powerful tool for monitoring, logging, and even controlling all the communication that takes place between the main processor and the radio. We present a rigorous evaluation of our prototype and demonstrate its utility using a variety of usage scenarios.

This paper presents modeling, design, and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems. The proposed design methodology is suitable for energy harvesting systems employed in low-cost applications, such as wireless sensor networks. Our approach is unique in achieving maximum output power by cross-layer optimization of poly-silicon solar cells (thickness, grain boundaries and cell configuration) and power converter circuits. Simulation results indicate that optimizing the solar cell along with the power converter improves the system output power by 16% compared to a baseline approach of optimizing the two components separately.

It is important to get an idea of the events occurring in an embedded wireless node when it is deployed in the field, away from the convenience of an interactive debugger. Such visibility can be useful for post-deployment testing, replay-based debugging, and for performance and energy profiling of various software components. Prior software-based solutions to address this problem have incurred high execution overhead and intrusiveness. The intrusiveness changes the intrinsic timing behavior of the application, thereby reducing the fidelity of the collected profile. Prior hardware-based solutions have involved the use of dedicated ASICs or other tightly coupled changes to the embedded node's processor, which significantly limits their applicability.In this paper, we present Aveksha, a hardware-software approach for achieving the above goals in a non-intrusive manner. Our approach is based on the key insight that most embedded processors have an on-chip debug module (which has traditionally been used for interactive debugging) that provides significant visibility into the internal state of the processor. We design a debug board that interfaces with the on-chip debug module of an embedded node's processor through the JTAG port and provides three modes of event logging and tracing: breakpoint, watchpoint, and program counter polling. Using expressive triggers that the on-chip debug module supports, Aveksha can watch for, and record, a variety of programmable events of interest. A key feature of Aveksha is that the target processor does not have to be stopped during event logging (in the last two of the three modes), subject to a limit on the rate at which logged events occur. Aveksha also performs power monitoring of the embedded wireless node and, importantly, enables power consumption data to be correlated to events of interest.Aveksha is an operating system-agnostic solution. We demonstrate its functionality and performance using three applications running on Telos motes; two in TinyOS and one in Contiki. We show that Aveksha can trace tasks and other generic events at the function and task-level granularity. We also describe how we used Aveksha to find a subtle bug in the TinyOS low power listening protocol.

Recent research on wireless network design has advocated the use of cross-layer modeling as a basis for optimizing network performance. However, it is not clear if cross-layer modeling is even viable in the presence of certain network characteristics, which raises questions about the real-world applicability of such optimization techniques. This paper attempts to assess the viability of cross-layer modeling for wireless mesh networks having three (commonly found) characteristics - asynchronous transmission, multi-hop communication, and ad-hoc connectivity. Our analytical study reveals that such modeling techniques have to solve an equation with higher order than a quintic equation in the case of a moderate queue size at each mesh node. As a result, our study uncovers a key finding that comprehensive cross-layer modeling for asynchronous, multi-hop, ad-hoc wireless mesh networks is simply not viable. Consequently, we point out a possible simplification of the model pertinent for non-congested wireless mesh networks and also perform an approximation analysis based on the simplification.

Thermal energy harvesting using micro-scale thermoelectric generators is a promising approach to alleviate the power supply challenge in ultra low power systems. In thermal energy harvesting systems, energy is extracted from the transducer using an interface circuitry, which plays a key role in the determining the energy extraction efficiency. This paper presents techniques for the systematic modeling, analysis, and design of interface circuitry used in micro-scale thermoelectric energy harvesting systems. We characterize the electrical behavior of a micro-scale thermoelectric transducer connected to a step-up charge pump based power converter and model the relationship between the transducer output voltage and the charge pump switching frequency. We model various power loss components inside the interface circuitry and present an analytical design methodology that estimates optimal parameter values for the interface circuitry. These parameter values lead to maximum net output power being delivered to the energy buffer. We have implemented various interface circuitries using IBM 65nm technology to verify our proposed models and methodology. Circuit simulation results show that the proposed methodology accurately estimates the maximum power point voltage of the system with an error of 3%.

Traffic gatekeeping, typically implemented using firewalls, is an essential functionality in today's networked computing systems such as desktop PCs. Traffic gatekeeping provides protection against a variety of over-the-network security attacks and can also be used to implement various communication resource management policies. With the development of technologies such as IPv6 and 6LoWPAN that pave the way for Internet-connected embedded systems and sensor networks, traffic gatekeeping will soon become a must-have for these systems as well. Towards this, we present Aegis, a lightweight, rule-based traffic gatekeeping framework for sensor networks. We present an overview of the Aegis architecture, its implementation, and two usage scenarios.

The field of green computing, which has gained tremendous importance and popularity over the past few years, has mainly focused on large computing systems such as server farms. This talk makes the case that it is equally important for green computing to be applied at the micro-scale, targeting the billions of embedded devices found everywhere around us. A promising start in this direction is to power embedded systems using environmental (renewable) energy sources such as solar, wind, vibration, etc., which raises the possibility of self-sustaining embedded systems. This tutorial highlights the challenges involved in architecting such self-sustaining embedded systems and discusses various hardware and software techniques for their efficient design and operation.

A detailed power analysis of a multi-radio mobile platform highlights the complex tradeoffs between the computation, storage, and communication subsystems. The particular mobile device, which does not include an LCD or other on-board display, can be used as a source for audio or video media files, or a source/sink for secure data transfers. A version of the device has been augmented with fine-grained power monitoring capability and used to obtain detailed measurements of power dissipation in the various subsystems. Analysis of these measurements sheds light on the power consumption characteristics of different applications, thereby providing hints to system designers about potential areas for optimization. Specifically, this work contrasts the power efficiency of the various wireless technologies supported by the system.

Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems being designed with battery considerations in mind, minimizing the energy consumed in on-chip interconnects becomes crucial. Further, the use of nanometer technologies is making it increasingly important to consider reliability issues during the design of SoC communication architectures. Continued supply voltage scaling has led to decreased noise margins, making interconnects more susceptible to noise sources such as crosstalk, power supply noise, radiation induced defects, etc. The resulting transient faults cause the interconnect to behave as an unreliable transport medium for data signals. Therefore, fault tolerant communication mechanism, such as Automatic Repeat Request (ARQ), Forward Error Correction (FEC), etc., which have been widely used in the networking community, are likely to percolate to the SoC domain. This paper presents a survey of techniques for energy efficient on-chip communication. Techniques operating at different levels of the communication design hierarchy are described, including circuit-level techniques, such as low voltage signaling, architecture-level techniques, such as communication architecture selection and bus isolation, system-level techniques, such as communication based power management and dynamic voltage scaling for interconnects, and network-level techniques, such as error resilient encoding for packetized on-chip communication. Emerging technologies, such as Code Division Multiple Access (CDMA) based buses, and wireless interconnects are also surveyed.