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In NAND flash storages, the invalidated pages could occupy the storage space until being erased. In order to preserve sustained write performance and storage capacity, the storage controller must eliminate these pages through garbage collection operations. However, the garbage collection operations may cause high computation overhead while selecting victim blocks, thereby resulting in the host system suffering from unendurable storage-access latency as well as performance degradation. In this paper, we propose an efficient garbage collection mechanism, which not only eliminates the computation overhead in victim block selection, but also improves responsiveness to the host requests by making the garbage collection operation preemptive.

Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as storage media in the embedded and computer system environments. In the case of reliability, however, there are many shortcomings in flash memory: potentially high I/O latency due to erase-before-write and poor durability due to limited erase cycles. To overcome these problems, a RAID technique borrowed from storage technology based on hard disks is employed. In the RAID technology, multi-bit burst failures in the page, block or device are easily detected and corrected so that the reliability can be significantly enhanced. However the existing RAID-5 scheme for the flash-based storage has delayed response time for parity updating. To overcome this problem, we propose a novel approach using a RAID technique in flash storage, called Flash-aware Redundancy Array. In this approach, parity updates are postponed so that they are not included in the critical path of read and write operations. Instead, they are scheduled for when the device becomes idle. For example, the proposed scheme shows a 19% improvement in the average write response time, compared to other approaches.

The communication efficiency plays a crucial role in achieving high system performance in many multimedia SoCs (System-On-Chips). Increased requirements on high bandwidth on-chip communication have led to the emergence of complicated communication architectures and algorithms. However, without thorough analysis of bandwidth requirements of applications, we tend to over-provision resources to avoid potential performance degradation. In this paper, we present a CBR-based traffic modeling technique along with a performance evaluation framework. By using this evaluation technique, we can estimate the sustained performance of on-chip communication infrastructure used in multimedia SoCs. The traffic behaviors of a multimedia application have been captured and analyzed to characterize individual operations which are modeled using traffic generators to replace hardware IPs in evaluation process. The simulation results show that this approach is also effective in discovering the peak performance of on-chip network and bandwidth allocation to IPs.

The use of NAND flash memory for building permanent storage has been increasing in many embedded systems due to properties such as non-volatility and low energy consumption. The persistent requirements for high storage capacity have given rise to the increase of bit density per cell as in multi-level cells but this has come at the expense of performance and has resulted in degradation of durability. In this paper, we introduce a complementary approach to boost the performance and durability of MLC-based storage systems by employing a non-volatile buffer that temporarily holds the data heading to MLCs. We also propose algorithms to efficiently eliminate unnecessary write and erase operations in MLCs by performing a pre-merge in the buffer. Our experiments show that the proposed approach can increase performance by up to 4 times and durability by 4 times by adding only a small hardware cost.