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This paper documents a systematic approach (RAMLFlask) to extending Web application frameworks (Flask) to include support for interface-description languages (IDLs such as RAML) and code generation.

Being an architectural style rather than a specification or a standard, the proper design of REpresentational State Transfer (REST) APIs is not trivial, since developers have to deal with a flood of recommendations and best practices, especially the proper application of the hypermedia constraint requires some decent experience. Furthermore, testing RESTful APIs is a missing topic within literature and especially, hypermedia testing is not mentioned at all. To deal with this state of affairs, we have elaborated a Model-Driven Software Development (MDSD) approach for creating RESTful APIs. As this project matured, we also explored the possibility of Model-Driven Testing (MDT). This work addresses the challenges of hypermedia testing and proposes approaches to overcome them with MDT techniques. We present the results of hypermedia testing for RESTful APIs using a model verification approach that were discovered within our research. MDT enables the verification of the underlying model of a RESTful API and ensuring its correctness before initiating any code generation. Therefore, we can prevent a poorly designed model from being transformed into a poorly designed RESTful API.

Data analytics has gained more and more focus during recent years and many data processing platforms have been developed. They all provide a powerful but often complex API that users have to learn. Furthermore, results can only be stored or printed, without any possibility for visualization. In this paper we present Piglet, a compiler for the high-level Pig Latin script language that generates code for various platforms like Spark, Flink, Storm, and PipeFabric. Piglet lets users write elegant code with extensions for SPARQL and RDF, as well as support for streaming data. An integration into the notebook-based frontend Zeppelin provides a homogeneous and interactive user interface for exploring, analyzing, and visualizing data from different sources and lets users share their scripts and results.

The security of hardware-software systems is at risk from a wide range of attack vectors that appear at various stages during the execution of machine code. The existing approaches for repairing software defects have numerous restrictions with respect to their applicability and functionality and to the range of vulnerabilities that can be identified and eliminated.We propose an approach for removing software errors in program code that is based on just-in-time compilation in a virtual execution environment. The virtual environment uses static, dynamic, and hybrid analyses of the intermediate representation of vulnerable code and re-compiles such code to be safe.The language of code annotations allows us to manage static and dynamic analyses and code transformations. We can change the level of analysis and the amount of time spent on such analyses by dynamically adapting the precision.

High-level programming languages and domain-specific languages can often benefit from the increased power efficiency of heterogeneous computing. OpenCL can serve as a compiler target for portable code generation and runtime management. By using OpenCL as the target platform, compiler writers can focus on more important, higher-level problems in language implementation. Such improved productivity can enable a proliferation of high-level programming languages for heterogeneous computing systems.The C++ programming language provides several high-level, developer-friendly features that are missing from OpenCL. These high-level features support software engineering practices and improve developer productivity. With the advent of OpenCL 2.0 and Heterogeneous System Architecture (HSA), more C++ language constructs can be efficiently mapped and executed on multi-core architectures. It is the compiler writerâAZs job to translate these features into the OpenCL constructs without incurring an excessive level of overhead.C++ AMP is a parallel programming extension to C++, and MulticoreWare have contributed to Clamp, an open source implementation. The compiler is based on Clang / LLVM, and could target multiple platforms such as OpenCL / SPIR / HSA. We present some important implementation techniques in this compiler, and we would also present how shared virtual memory, platform atomics could allow more generic C++ codes to leverage multi-core architectures.

Domain-Specific Modeling (DSM) has proven to be a viable solution to the challenges related to abstraction mismatches between the problem and solution spaces. In many cases, DSM assists in the generation of final products from high-level models that are specific to a domain in terms of abstractions and representation. This automation is possible because both the language and generators are tailored for one domain. This paper introduces DSM and describes the related workshop at SPLASH 2014 (21 October 2014, Portland, Oregon).

Compilers for data-parallel languages use data distribution specifications to guide code generation for distributed-memory machines. Our 1994 paper described how to generate efficient code for programs that employ block-cyclic data distributions. In subsequent work at Rice University, Darte, Mellor-Crummey, Fowler, and Chavarria-Miranda developed a more general form of block-cyclic partitionings known as generalized multipartitionings. Generalized multipartitionings provide some additional balance properties that make them useful for parallelizing computations that solve recurrences along spatial dimensions. These partitionings were subsequently implemented in Rice University's dHPF compiler for High Performance Fortran. In the years since, the field has changed in many ways; however, variants of block-cyclic data distributions are still used today by modern parallel programming models, algorithms, and compilers. Original paper: http://dx.doi.org/10.1145/181181.181572

Context-oriented programming (COP) provides a very intuitive way to handle run-time behavior varying in several dimensions. However, COP usually requires major language extensions and implies a considerable performance loss. To avoid language extensions we propose to specify program execution environments as contextual values in separate units. A tool translates such specifications into C++ classes usable in the rest of the program. Without the need of multiple dispatch, the performance can largely profit from simple caching. Furthermore, it is easy to support debugging and store contextual values in configuration files.

JavaScript is widely used in Web applications because of its flexibility and dynamic characteristics. However, the latter (e.g., runtime code generation and dynamic object behavior) pose challenges for program understanding, security, etc. We have designed the JavaScript Blended Analysis Framework, a program analysis framework that combines dynamic and static analyses. JSBAF expands the capability of static analysis for the dynamically generated code and variadic functions. We also present a novel context-sensitive points-to analysis that more precisely models JavaScript objects. Empirical results on popular JavaScript websites show that our analyses are substantially more accurate than existing approaches.

We describe a parallel programming tool for scheduling static task graphs and generating the appropriate target code for message passing MIMD architectures. The computational complexity of the system is almost linear to the size of the task graph and preliminary experiments show performance comparable to the "best" hand-written programs.

Websites need to be displayed on a panoply of different devices today, but most websites are designed with fixed widths only appropriate to browsers on workstation computers. We propose to programmatically rewrite websites into responsive formats capable of adapting to different device display sizes. To accomplish this goal, we cast retargeting as a cross-compilation problem. We decompose existing HTML pages into boxes (lexing), infer hierarchical structure between these boxes (parsing) and finally generate parameterized layouts from the hierarchical structure (code generation). This document describes preliminary work on ReMorph, a prototype 'retargeting as cross-compilation' system.

High-level productivity languages such as Python, Matlab, and R are popular choices for scientists doing data analysis. However, for today's increasingly large datasets, applications written in these languages may run too slowly, if at all. In such cases, an experienced programmer must typically rewrite the application in a less-productive performant language such as C or C++, but this work is intricate, tedious, and often non-reusable. To bridge this gap between programmer productivity and performance, we extend an existing framework that uses just-in-time code generation and compilation. This framework uses the SEJITS methodology, (Selective Embedded Just-In-Time Specialization [11]), converting programs written in domain specific embedded languages (DSELs) to programs in languages suitable for high performance or parallel computation.We present a Python DSEL for a recently developed, scalable bootstrapping method; the DSEL executes efficiently in a distributed cluster. In previous work [18, Prasad et al. created a DSEL compiler for the same DSEL (with minor differences) to generate OpenMP or Cilk code. In this work, we create a new DSEL compiler which instead emits code to run on Spark [16], a distributed processing framework. Using two example applications of bootstrapping, we show that the resulting distributed code achieves near-perfect strong scaling from 4 to 32 eight-core computers (32 to 256 cores) on datasets up to hundreds of gigabytes in size. With our DSEL, a data scientist can write a single program in serial Python that can run "toy" problems in plain Python, non-toy problems fitting on a single computer in OpenMP or Cilk, and non-toy problems with large datasets on a multi-computer Spark installation.

International audience; Formal methods have emerged as an alternative approach to ensuring the quality and correctness of the high con - dence critical systems, overcoming limitations of the traditional validation techniques such as simulation and testing. This paper presents a methodology for developing the critical systems from requirement analysis to automatic code generation with standard safety assessment approach. This methodology combines the re nement approach with various tools including veri cation tool, model checker tool, real-time animator and nally, produces the source code into many languages using automatic code generation tools. This approach intends as a contribute to further the use of formal techniques for developing critical systems with high integrity and to verify the complex properties, which help to discover the potential problems. Assessment of the proposed methodology is given through developing a standard case study: the cardiac pacemaker.

In this position paper, we address issues of the development of correct-by-construction components for GeneAuto a qualifiable (according to DO178B-ISO26262 recommendations) automatic code generator. It transforms Simulink, Stateflow and Scicos models to MISRA C code for safety critical systems. This approach which combines classical development process and formal specification and verification using proof-assistants, led to preliminary fruitful exchanges with certification authorities. We have derived formal specifications from classical user and tools requirements, formally implemented and verified the correctness of some components of the code generator. The block sequencer case study has been successfully applied to real-size industrial use cases from various transportation domain partners and led to requirement errors detection and a correct-by-construction implementation with reduction of test effort.

Static analysis is often performed on source code where intervals -- possibly the most widely used numeric abstract domain -- have successfully been used as a program abstraction for decades. Binary code on microcontroller platforms, however, is different from high-level code in that data is frequently altered using bitwise operations and the results of operations often depend on the hardware configuration. We describe a method that combines word- and bit-level interval analysis and integrates a hardware model by means of abstract interpretation in order to handle these peculiarities. Moreover, we show that this method proves powerful enough to derive invariants that could so far only be verified using computationally more expensive techniques such as model checking.

Device Independence is a concept based on the idea of making services, applications and contents available to users regardless of the device used to enjoy them. One of the problems for developers of mobile applications is the number of different mobile platforms in the market. Therefore, a software platform to generate an application for as many platforms as possible would increase enormously the number of potential users. We propose a framework (DIMAG: Device Independent Mobile Application Generation framework) to generate mobile applications for multiple software platforms by means of a declarative description of the application. Besides, the generation of an application with this framework takes into account additional requirements like the need of mobile applications to consume and provide data from and to remote machines, or the dynamic load of the classes for code generation for a given mobile platform after identification of the device demanding a copy of the application. The generation of two simple but exemplifying applications shows the feasibility of DIMAG as a framework to relieve the problem of device fragmentation for mobile developers.

This paper describes timed transition in pCharts, a variation of statecharts extended with probabilistic transitions, costs/rewards, and state invariants. Timed transitions with nondeterministic and stochastic timing can be used for the specification and analysis of real-time systems. We present a translation scheme for timed transition of pCharts into probabilistic timed automata (PTA) and executable C code, as implemented in our tool pState. To illustrate the development process, we analyze the power consumption of a radio-frequency identification (RFID) tag and generate code for the PIC micro-controller.

We describe the Marama suite of meta-tools. This Eclipse-based toolset permits rapid specification of notational elements, meta-models, view editors and view-model mappings. It has a novel set of behavioural specification tools for both visual and model level behaviours. An integrated mapping tool provides model transformation and code generation support. The toolset has been applied to several significant application development tasks and has undergone a variety of evaluations.

Developers perform small-scale reuse tasks to save time and to increase the quality of their code. Due to the small scale of such tasks, the overhead in reusing source code can quickly outweigh the benefits. Existing approaches focus on locating source code for reuse but do not support the integration of the located code within the developer's system, thereby leaving the developer with the burden of performing these steps manually. This paper presents a tool, called Jigsaw, that uses the developer's context to help integrate the reused source code into the developer's own source code.

Association is an important relationship that is supported in both UML and entity relationship database modeling tools. However, there is no language or library support in current object-oriented languages for implementing an association relationship. Instead, a complex implementation using references or collections of references must be handcrafted and laboriously maintained each time an association relationship is needed. In this paper, we develop an approach to supporting the association relationship through the design of a reusable class library that hides most of the complexity and guarantees that the consistency of the relationship is maintained automatically. Our current library implementation in C# draws on generic types with runtime type instantiation, runtime reflection on type parameters, annotations on classes, and runtime code generation. This set of language features seems to be necessary to provide effective support for association relationships.

ProVotE is a two-phase project aiming at actuating art. 84 of law 2 -- 5/3/2003 of the Autonomous Province of Trento (Italy), which promotes the introduction of e-voting systems for the next provincial elections in Trentino (Nov. 2008).During the first phase of the ProVotE project we built jprovote, a Java/Linux e-voting system. The jprovote system has been used with experimental value by more than 11000 voters during local elections held in various municipalities of Trentino (Italy).A critical component of jprovote is its core logic, that is responsible of controlling the overall behavior of the e-voting machine during an election. In order to simplify its development and to allow for formal verification of this critical component we developed FSMC+.FSMC+ is a compiler that takes as input a subset of UML Statecharts and produces the corresponding Java and NuSMV code (NuSMV is a model checker developed at ITC-irst). Support for parameters in events, complex expressions in guards, and support to nested states are some of the distinguishing features of FSMC+.In this paper we present FSMC+ and we show how we used it for the development and the verification of the ProVotE e-voting machine. Even though FSMC+ has been specifically created to ease the development of jprovote, we believe the approach and the tool we developed to be general enough to be used in other applications.

Heterogeneous MPSoCs present unique opportunities for emerging embedded applications, which require both high-performance and programmability. Although, software programming for these MPSoC architectures requires tedious and error-prone tasks, thereby automatic code generation tools are required. A code generation method based on fine-grain specification can provide more design space and optimization opportunities, such as exploiting fine-level parallelism and more efficient partitions. However, when partitioned, fine-grain models may require a large number of inter-processor communications, decreasing the overall system performance. This paper presents a Simulink-based multithread code generation method, which applies Message Aggregation optimization technique to reduce the number of inter-processor communications. This technique reduces the communication overheads in terms of execution time by reduction on the number of messages exchanged and in terms of memory size by the reduction on the number of channels. The paper also presents experiment results for one multimedia application, showing performance improvements and memory reduction obtained with Message Aggregation technique.

This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly parallel programming model, programmers maximize algorithm- level parallelism, express their parallel algorithms by asserting high-level properties on top of a traditional sequential programming language, and rely on parallelizing compilers and hardware support to perform parallel execution under the hood. In such a model, compilers and related tools require much more advanced program analysis capabilities and programmer assertions than what are currently available so that a comprehensive understanding of the input program's concurrency can be derived. Such an understanding is then used to drive automatic or interactive parallel code generation tools for a diverse set of parallel hardware organizations. The chip-level architecture and hardware should maintain parallel execution state in such a way that a strictly sequential execution state can always be derived for the purpose of verifying and debugging the program. We argue that implicitly parallel programming models are critical for addressing the software development crises and software scalability challenges for many-core microprocessors.

In this paper we propose a framework for the design and development of adaptive Web applications. The framework leverages on the integration of two well established approaches: a conceptual model, complemented with a CASE tool for automatic code generation, and a language for expressing ECA rules, supported by an engine for rule execution. Such integration leads to a versatile and flexible adaptivity environment, whose advantage is twofold: on one hand, conceptual modeling and automatic code generation support an efficient development process; on the other hand a detached rule engine allows us to widen the set of adaptivity requirements that can be handled and to overcome some limitations of current modeling approaches.

The present visual language supports the imperative programming style and claims to improve program comprehension by resemblance. It can be characterized as follows: 1) Its scope is the static description of code, data and flow control as well as of the surrounding architecture including classes, components, modules, up to systems. 2) Its abstraction level is next to that of C++ including templates and the standard template library and allows straight-forward code generation. 3) The visualization is specified by editing boxes, bars, arrows and textual labels on a drawing area with relatively fixed editing positions. 4) The interface of the visualization is the drawing area itself, enabling further editing or navigating through the program by clicking on the bars, boxes and labels or by defining views via textual or topological queries. 5) The presentation of the visualization is by a (still hypothetical) wall-projection of the virtual drawing area.

How to decompose or map data of programs automatically onto scalable parallel processors is a key issue in developing parallelizing compilers in DSM architecture. Data locality is crucial for parallelized programs to achieve high performance. Based on a linear inequalities mathematical model a formal specification of an optimized data decomposing algorithm and its implementation in C++ are presented. The algorithm enhances data locality and minimizes communication. Experimental results indicate that the algorithm improves the performance of parallelized programs significantly.

OMEGA is a model-driven code generation approach based on Executable UML enhanced with extension information provided by metamodel hierarchies. It is domain-specific but can easily incorporate new or related domains. In this experience report, we describe the challenges encountered during the implementation of a code-generation facility for the J2EE platform.

This paper presents a prototype environment for HW/SW co--design of embedded systems based on the Unified Modeling Language (UML) and SystemC. The environment supports a model-driven SoC design methodology which provides a graphical high-level representation of hardware and software components, and allows either C/C++/SystemC code generation from models and a reverse engineering process from code to graphical UML models.

This paper addresses conceptual modeling and automaticcode generation for Rich Internet Applications, a variant ofWeb-based systems bridging desktop and thin-client Webinterfaces. We show how classical Web modeling conceptsare not enough to capture the specificity of RIAs, extend anexisting Web modeling language, and provide an implementationof a CASE tool for visual modeling and code generationfrom RIA-aware specifications. Experimentation of theproposed approach in real-world scenarios is also reported.

Nowadays, the system-on-a-chip (SoC) has integrated more processors onto a single chip. Applications are also consisting of multiple (sub) tasks that are presented as different source code which can be partly executed concurrently. However, the subtask-level parallelism inside a single task is often too limited to fully utilize all the parallel processors and results in many slacks on processors. To better use the processors, subtasks of multiple tasks will have to be executed in an interleaving fashion. This paper proposes design-time algorithms to interleave subtasks based on the separated schedules of tasks. This interleaver can be considered as part of a hierarchical scheduler to steer the code generation of very complex applications with many tasks. The scheduling experiments show that the execution time can be shortened by 20%-30% when interleaving two tasks against the sequential execution without subtask interleaving. Moreover, the differences between the solutions given by our scheduling algorithm and the optimal solutions are less than 6% for up to 20 subtasks.

When coding to a framework, developers often become stuck, unsure of which class to subclass, which objects to instantiate and which methods to call. Example code that demonstrates the use of the framework can help developers make progress on their task. In this paper, we describe an approach for locating relevant code in an example repository that is based on heuristically matching the structure of the code under development to the example code. Our tool improves on existing approaches in two ways. First, the structural context needed to query the repository is extracted automatically from the code, freeing the developer from learning a query language or from writing their code in a particular style. Second, the repository can be generated easily from existing applications. We demonstrate the utility of this approach by reporting on a case study involving two subjects completing four programming tasks within the Eclipse integrated development environment framework.

The combination of Unified Modeling Language (UML) and SystemC has led to an object-oriented high-level design automation methodology. In this paper, a novel bi-directional UML-SystemC translation tool UMLSC is proposed. Specifically, a set of principles for modeling SystemC design in UML and an algorithm for UML-SystemC bi-directional translation are addressed. The principles and the algorithm are integrated into UMLSC* which provides a smooth link between visual specification, implementation and verification. An implementation example is given to verify the effectiveness of the proposed principles and the algorithm.

Developing Eclipse plug-ins often involves the creation of data structures and corresponding data processing code. In developing eAssignment, an Eclipse-bases application to support electronic programming exercises, we identified several issues with implicit models of data structures and hand-written code needed to access them. In this paper, we report on our experiences of using the Eclipse Modeling Framework to overcome these shortcomings.

Mining software repositories at the source code level can provide a greater understanding of how software evolves. We present a tool for quickly comparing the source code of different versions of a C program. The approach is based on partial abstract syntax tree matching, and can track simple changes to global variables, types and functions. These changes can characterize aspects of software evolution useful for answering higher level questions. In particular, we consider how they could be used to inform the design of a dynamic software updating system. We report results based on measurements of various versions of popular open source programs. including BIND, OpenSSH, Apache, Vsftpd and the Linux kernel.

Code generators are increasingly used in an industrial context to translate graphical models into executable code. Since the code is often deployed in safety-related environments, the quality of the code generators is of paramount importance. In this paper, we will present and discuss state-of-the-art techniques for safeguarding automatic code generation applied in model-based development.

We consider the type inference problems in a compositional design environment where the components are automatically instantiated from pre-existing C++-based intellectual property (IP) libraries. We present a component integration language based on scripting for design specification. Our focus is the architectural aspects in the specification that use aggregation - as opposed to the more commonly used inheritance - for composition of components. Our approach simplifies architectural specification by employing a type inference and type management environment. We show that the type inference problem is NP-complete. We present a heuristic based on code generation and parameterization to solve the type inference for IP selection in our C++-based composition environment. We have implemented the composition and type management in the BALBOA framework. The results show the utility of our approach.

This paper studies the use of a reconfigurable architecture platform for embedded control applications aimed at improving real time performance. The hw/sw codesign methodology from POLIS is used. It starts from high-level specifications, optimizes an intermediate model of computation (Extended Finite State Machines) and derives both hardware and software, based on performance constraints. We study a particular architecture platform, which consists of a general purpose processor core, augmented with a reconfigurable function unit and data-path to improve run time performance. A new mapping flow and algorithms to partition hardware and software are proposed to generate implementations that best utilize this architecture. Encouraging preliminary results are shown for automotive electronic control examples.

Meaningful application benchmarking is crucial to processor design space exploration and compiler development. Many recent studies in the embedded processor domain have used reference telecommunications C programs which were originally intended to verify product compliance with a standard. In this paper, we demonstrate that telecommunications reference applications include a significant amount of superfluous code that skews a wide variety of experiments related to code size. A categorization of extra code is presented, and it is also demonstrated that benchmark inputs do not test broad usage patterns that might exist in a real system. It is shown that care must be taken in future studies to properly construct benchmarks which match the intended purpose of the target system and to provide inputs that more thoroughly exercise paths through telecommunications applications.

One of the important issues in embedded system design is to optimize program code for the microprocessor to be stored in ROM. In this paper, we propose an integrated approach to the DSP address code generation problem for minimizing the number of addressing instructions. Unlike previous work in which code scheduling and offset assignment are performed sequentially without any interaction between them, our approach tightly couples the offset assignment problem with code scheduling to exploit scheduling on minimizing addressing instructions more effectively. We accomplish this by developing a fast but accurate two-phase procedure which, for a sequence of code schedules, finds a sequence of memory layouts with minimum addressing instructions. Experimental results with benchmark DSP programs show improvements of 13%-33% in the address code size over Solve-SOA/GOA.

The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the HW / SW partitioning decision needs to be made prior to refining the system description. With OCAPI-xl, we developed a methodology in which the partitioning decision can be made anywhere in the design flow, even just prior to doing code-generation for both HW and SW. This is made possible thanks to a refinable, implementable, architecture independent system description. The OCAPI-xl model was used to develop a stand alone, networked camera, with on-board GIF engine and network layer.

Traditionally, compiler technology has focused on the generation of code with the goal of improving performance for a variety of applications running on general-purpose processor architectures. In the embedded system space, compiler technology is faced with many new challenges, including: code generation for specialized architectural features, requireing a highly flexible degree of retargetability; memory-aware code generation that exploits the timing and structure of the embedded system's memory organization; optimizing software to meet both real-time and performance constraints; energy- and power-aware software generation, both from the context of energy minimization, as well as power modulation; code size minimization for memory-constrained embedded systems; coarse-grain transformations for tightly-coupled, memory-constrained multi-processor architectures; and interaction with the operating system for active management of embedded system resources. This paper discusses new directions for compiler technology, surveys some of the current research efforts and illustrates proposed solutions to selected issues.

The ever increasing complexity of signal processing applications and the desire to reduce the time to market demands efficient compilation techniques for programmable Digital Signal Processors (DSPs). Because the instruction sets of VLIW processors are more regular and orthogonal then the instruction sets of the traditional DSPs, they tend to be more compiler friendly. However in order to improve the maximal clock frequency, the power efficiency and the code density, several register files are used in the newer generation of VLIW processors instead of just one large register file. The use of several register files and partial connected networks leads, for example, to the problem that a result stored in a register file can not be accessed by all the functional units in the processor. This makes the assignment of operations to functional units a difficult task for the compiler.This paper describes the constraint analysis based operation assignment techniques intended to deal with processors with distributed register files and partially connected networks. The assignment techniques have been implemented in our code generation tool FACTS [8]. This tool is intended for the generation of an operation assignment, a register binding and a schedule of folded loops that satisfy the specified timing constraints. Our approach is based on satisfaction of constraints which makes it different from the optimisation based operation assignment techniques [4][2][3] which are known from literature. The operation assignment technique is based on the modeling of the assignment search space in a conflict graph. Pruning of this conflict graph prevents decisions that inevitably lead to solutions that do not satisfy the timing constraints. If after pruning infeasibility is detected, backtracking of assignment decisions is performed. In order to obtain a tight coupling between the assignment phase and the schedule phase information is derived from the conflict graph which is used to prune the schedule search space and information from the schedule search space is incorporated in the conflict graph. Automatic insertion of copy operations for moving intermediate values from one register file to another register files is not supported. However the use of a shared global bus in the processor guarantees that at least one direct communication path from a producing functional unit to a consuming functional unit exists and therefore the use of copy operations is not necessary.

DSPs are typically equipped with indirect addressing modes with auto-increment and auto-decrement, which provide efficient address arithmetic calculations. Such an addressing mode is maximally utilized by careful placement of variables in storage, thereby reducing the amount of address arithmetic instructions. Finding proper placement of variables in storage is called storage assignment problem and the result highly depends on the access sequence of variables. This paper suggests statement scheduling as a compiler optimization step to generate a better access sequence. Experimental results show 3.6% improvement on the average over naive storage assignment.

We address software optimization for embedded control systems. The Esterel language is used as the front-end specification; Esterel compiler v6 is used to partition the control circuit and data path; the resulting intermediate representation of the design is a control-data network. This paper emphasizes the optimization of the control circuit portion and the code generation of the logic network. The new control-data network representation has four types of nodes: control, multiplexer, predicate and data expression; the control portion is a multi-valued logic network (MV-network). We use an effective multi-valued logic network optimization package called MVSIS for the control optimization. It includes algebraic methods to perform multi-valued algebraic division, factorization and decomposition and logic simplification methods based on observability don't cares. We have developed methods to evaluate a control-data network based on both an MDD and sum-of-products representation of the multi-valued logic functions. The MDD-based approach uses multi-valued intermediate variables and generates code according to the internal BDD structure. The SOP-based code is proportional to the number of cubes in the logic network. Preliminary results compare the two approaches and the optimization effectiveness.

Efficient implementation of DSP applications are critical for many embedded systems. Optimising compilers for application programs written in C, largely focus on code generation and scheduling which, with their growing maturity, are providing diminishing returns. This paper empirically evaluates another approach, namely high level source to source transformations. High level techniques were applied to the DSPstone benchmarks on 3 platforms: TriMedia TM-1000, Texas Instruments TMS320C6201 and the Analog SHARC ADSP-21160. On average, the best transformation gave a factor of 2.43 improvement across the platforms. In certain cases a speedup of 5.48 was found for the SHARC, 7.38 for the TM-1 and 2.3 for the C6201. These preliminary results justify further investigation into the use of high level techniques for embedded compilers.

Due to an increasing need for flexibility, embedded systems embody more and more programmable processors as their core components. Because of silicon area and power considerations, the corresponding instruction sets are often highly encoded to minimize code size for given performance requirements. This has hampered the development of robust optimizing compilers because the resulting irregular instruction set architectures are far from convenient compiler targets. Among others, they introduce a strong phase coupling between the tasks of instruction selection and scheduling. Traditional methods perform these tasks in different phases, thereby yielding inferior schedules. In this paper, we present an approach that reduces the need for explicit instruction selection by transferring constraints implied by the instruction set to static resource constraints. All resulting schedules are then guaranteed to correspond to a valid implementation with available instructions. We demonstrate a practical way to identify and construct a static resource model from a given instruction set. Experimental results show the efficacy of our approach.

In this paper we propose a procedure to generate code with minimum number of addressing instructions. We analyze different methods of generating addressing code for scalar variables and quantify the improvements due to optimizations such as offset assignment, modify register optimization and address register assignment. We propose an offset assignment heuristic that uses k address registers, an optimal dynamic programming algorithm for modify register optimization, and an optimal formulation and a heuristic algorithm for the address register assignment problem.

In the design of application-specific instruction set processors (ASIPs) a tight interplay between architecture and compiler is of utmost importance. Here, we try to characterize the design space of both compiler frontend (intermediate code optimization) and backend (architecture-specific code generation) that is used in order to do Architecture/Compiler Co-Exploration for the search of optimal architecture/compiler combinations. The described results present the state of development of such a framework called BUILDABONG [3].