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A cipher core has been implemented, which is dedicated to a 64-bit block, 128-bit key, dynamically reconfigurable hardware-based cipher, called "Chameleon", in which two 32-cell, 8-context dynamically reconfigurable hardware units are employed to generate new subkeys for each of the 16 iterations in the encryption/decryption process. The proposed architecture has been implemented by 0.6 um CMOS3LM technology, using 65.6K transistors and attaining a maximum throughput of 317.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryption/decryption applications in the mobile computing.

A high performance and low power architecture is devised for a 4 Mbps infrared wireless communication system dedicated to mobile computing. In this architecture 4PPM (4-Pulse Position Modulation) infrared signals detected by an infrared receiver are digitized into TTL interface level pulses, and the digitized pulses are demodulated by a 1-bit digital demodulator. To extend the range of the link length, a 4PPM demodulator is synthesized to implement a demodulation algorithm which is constructed so as to accommodate the output tolerance of the infrared receiver. A experimental results show that the proposed 4 Mbps infrared communication system can achieve an error free link in the range of 0-140 cm at power consumption of 245 mW and 65 mW for transmitting and receiving, respectively. The communication controller is integrated in a 0.6 /spl mu/m CMOS standard-cell chip, which contains 10,015 transistors on a 12 mm/sup 2/ die.

A low-power H.263 video codec core dedicated to low bitrate visual communication is described. A number of sophisticated architectures have been devised by attempting not only to minimize the total chip area but also to reduce the power consumption to such an extent that the operation frequency can be slowed down to 15 MHz. As a result, the whole encoding and decoding facilities of an H.263 video codec core have been integrated in the die area of 6.54 mm/sup 2/ by means of a 0.35 /spl mu/m CMOS technology, with the dissipation of 146.60 mW from a single 3.3 V supply.

A low-power processor architecture is described dedicatedly for embedded application programs by means of an object code compression approach. This approach unifies duplicated instructions existing in the embedded program and assigns a compressed object code to such an instruction. An instruction decompressor is constructed so as to generate an object code from each compressed object code (pseudo code) input. A single-chip implementation of this decompressor together with a processor core can effectively reduce the bandwidth required for the I/O interface. To demonstrate the practicability of the proposed approach, experiments are applied to an embedded processor ARM610 which attains 62.5% code compression, and hence 42.3% of the power consumption of instruction memory can be reduced.

A layout approach is attempted dedicatedly for MMICs (monolithic microwave integrated circuits), on which predominant layout elements are transistors, resistors, capacitors, inductors, coplanar waveguides, T junctions, etc., formed by the GaAs fabrication process. The layout issue typical of such MMICs consists essentially in how to realize a single layer placement of different shapes of layout elements under a variety of spacing, orientating, and shaping constraints. Each layout element is modeled to simplify placement tasks subject to different placement constraints, and then a set of the interconnection requirements among elements is represented by a graph, to which a planarization algorithm is effectively applied. As a result of this planarization, a placement procedure is constructed mainly by repeated application of a merging scheme. A number of experimental results are also shown to demonstrate the practicability of the described layout approach.

A high performance design methodology is described for a digital demodulator, which is intended for the noise immune wireless infrared data communication. In this methodology, ASK (Amplitude Shift Keying) infrared signals detected by a photo detector are digitized into two logic-level pulses by an infrared receiver, and the demodulation of the digitized signals is implemented by a new architecture. On account of the interference with optical noises from fluorescent lamps, an ASK receiver is realized by a 1-bit digital demodulator, which is designed with use of a high level synthesis tool COMPASS so as to implement an algorithm for removing the noises. A part of experimental results is also shown to demonstrate the practicability.

A multimicrocomputer system is described, stressing mainly software and hardware architectures, which has been constructed mainly for image creation. This system is distinctive mainly in that (i) 64 unit computers are interconnected with a root computer, each of equal performance, such that a number of unit computers constitute a pipelined computer and such pipelined computers work in parallel, all controlled by the root computer, and (ii) an intercomputer memory swapping unit is introduced, which is to be linked with a pair of unit computers to transfer a great amount of data at a time from one to the other through the use of a bus exchange switch.

The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multi-phase clocking system, and occupies ordinarily a considerable part of chip area. In this paper, a layout system for this portion of an LSI is described, which is constructed on the basis of a set of optimization heuristics. Experimental results of the layout system are also shown so as to reveal that the random logic portion can be realized in much the same area as can be done by manual layout.