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Surface roughness characterization of plasma textured polycrystalline silicon solar wafer is estimated at different DC potentials by image processing. Laser speckle based Fractal dimension is a cross-scale surface descriptor of roughness. This investigation shows that surface roughness of the samples increases due to plasma processing in the measured range.

Femtosecond laser sulfur hyperdoped silicon (fs-hSi) is capable of absorbing photons in the infrared spectral range while simultaneously exhibiting negligible reflection. However, laser processing creates detrimental amorphous and polycrystalline silicon surface layers impairing electronic properties, especially reducing minority charge carrier lifetimes. This paper demonstrates how to selectively remove these disadvantageous layers by ion beam etching, while crystalline IR-absorbing silicon underneath is left. The increase in silicon crystallinity is quantified by laterally probing the fs-hSi samples with Raman spectroscopy.

This paper demonstrates a polycrystalline silicon avalanche mode light-emitting device. The unique N+PN+PN+ cascade structure is designed to enhance light intensity via carrier injection engineering, in which the minority carriers are injected from the forward-biased junction to the light emission junction. Visible light can be observed at the reverse-biased PN junctions when the device operating voltage exceeds 20 V. In particular, the phonon-assisted indirect interband recombination of carriers with excess energy may be the main mechanism of photon emission. A specific junction model is proposed to explain that the light intensity peaks are generated primarily via carrier injection. Comparing the spectral measurements of a single polysilicon N+P junction device and the proposed cascade device shows that the strategy of improving the luminous intensity via carrier injection engineering is feasible and effective.

MEMS sensors based on magnetoelectric composites have attracted great interest due to their capability to detect weak magnetic fields, showing high potential in applications like biomagnetic field detection and magnetic particle imaging. This paper reports on a scandium aluminum nitride thin film-based MEMS magnetoelectric sensor. The sensor consists of a polycrystalline silicon cantilever with a size of 1000 μm × 200 μm covered by a piezoelectric Al0.73Sc0.27N and a magnetostrictive (Fe90Co10)78Si12B10 thin film. The performance of the presented sensor is investigated based on the magnetoelectric (ME) voltage coefficient, voltage noise density, and limit of detection and compared to the characteristics of the aluminum nitride thin film-based ME sensor with the same layout and fabrication technology. By using an Al0.73Sc0.27N thin film with a higher piezoelectric activity instead of AlN in MEMS ME sensors, the ME voltage coefficient of (1334 ± 84) V/cm Oe in resonance is almost double, thereby lowering the requirements for the electronic system. The limit of detection of (60 ± 2) pT/Hz0.5 remains unchanged due to the dominant thermomechanical noise in resonance.

International audience; Passivating the contacts of crystalline silicon (c-Si) solar cells with a polycrystalline silicon layer (poly-Si) on a thin oxide (SiOx) film allows to decrease the recombination current at the metal/c-Si interface. In this study, an ex-situ doping method of poly-Si is proposed, involving a SiOxNy:B layer as a dopant source. In this study, we compare the properties (crystallinity of the deposited layer, doping profile and surface passivation properties) of the resulting ex-situ doped poly-Si(B) layer with our in-situ doped reference.

The performance analysis and evaluation of a real grid-connected photovoltaic (PV) system operating under the mild continental climate condition of Kosovo are conducted in this paper. The PV system is installed on a flat roof of the laboratory building at the Faculty of Electrical and Computer Engineering. With fixed monocrystalline silicon (m-Si) and polycrystalline silicon (p-Si) module types with installed capacities of 1.76 kWp and 2.16 kWp respectively, inclined at an angle of 45 °C, facing south and through two solar inverters, the latter feds the low voltage distribution grid with electricity. Performance and meteorological data for each type of module were collected and analyzed for the period between December 2014 and November 2015. The m-Si PV modules have shown higher performance compared to p-Si PV modules. Electricity production during the monitoring period was 1286.57 kWh/kWp from p-Si modules and 1328.21 kWh/kWp from m-Si modules. The annual average daily final yield (Yf), the annual average value of the performance ratio, and system efficiency (ηsys) for the p-Si PV modules were found to be 3.53 kWh/kWp/day, 80%, and 11.67%, respectively. In addition, the corresponding values for the m-Si modules were 3.64 kWh/kWp/day, 84%, and 12.78%, respectively. Furthermore, a comparative analysis of the performance of the photovoltaic system under study with other photovoltaic systems installed in various countries worldwide was carefully investigated and presented in this paper. © 2018. This is the authors’ accepted and refereed manuscript to the article.

A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier effects. The program/erase operation of the 1T-DRAM is performed by trapping/detrapping charges in GB traps. The trapped charges cause variations in the grain energy barrier of the storage region, which forms the sensing margin of the 1T-DRAM. The proposed cell achieved a high sensing margin of 4.45 μA/μm and a long retention time (>100 ms) at a high temperature of 373 K (100 °C).

Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) are recently used in many display applications due to its high mobility and high stability. However, its processing at low temperature causes defects which affect charge carrier mobility. So, it is essential to completely understand the effects of defects on charge transport mechanism. In this paper, experimental results are presented to investigate the charge carrier mobility of LTPS device. Furthermore, based on the theoretical model, the charge transport characteristic for LTPS has been interpreted. Our results show that, at low gate voltage, the charge transport of LTPS TFT displays multiple trapping and release mechanism, while free charge carrier transport mechanism at high gate voltage.

For effective utilization of solar energy, performance monitoring of photovoltaic (PV) systems is required. Two important research goals are to maximize the power output from PV systems and further reduce the economic losses. This paper proposes a model using a clustering-based technique to evaluate the degradation of PV panels with different topologies. Here, the performance ratio (PR) of the PV panels is estimated without physical inspection on-site, making the proposed model beneficial for real-time estimation of the PR and in turn for more robust forecasting of the PV power output. The present work utilizes the segmental K-means clustering technique to obtain clusters of input meteorological data sharing similar features. Various forms of meteorological data, including temperature, relative humidity, wind speed, dew point, solar radiation, and sunshine hours, are given as the input, and solar power data are the output of the proposed model. The proposed model calculates the degradation in output solar power in terms of PR for panels with three different topologies, namely, amorphous silicon (a-Si), polycrystalline silicon (p-Si), and hetero-junction with an intrinsic thin layer (HIT), over a period of three years. The degradation rate produced by a-Si technology was lowest, and it was highest for HIT technology. The results obtained showed good agreement with the standard method used for performance evaluation in a similar earlier study. The proposed model has the advantage over other methods that real-time estimation is possible, as this method does not require physical inspection and imaging, which is essential in other techniques.

Of all the materials available to create carrier-selective passivating contacts for silicon solar cells, those based on thin films of doped silicon have permitted to achieve the highest levels of performance. The commonly used chemical vapour deposition methods use pyrophoric or toxic gases like silane, phosphine and diborane. In this letter, we propose a safer and simpler approach based on physical vapour deposition (PVD) of both the silicon and the dopant. An in-situ doped polycrystalline silicon film is formed, upon annealing, onto an ultrathin SiOx interlayer, thus providing selective conduction and surface passivation simultaneously. These properties are demonstrated here for the case of hole-selective passivating contacts, which present recombination current densities lower than 20 fA/cm2 and contact resistivities below 50 mΩ cm2. To further demonstrate the PVD approach, these contacts have been implemented in complete p-type silicon solar cells, together with a front phosphorus diffusion, achieving an open-circuit voltage of 701 mV and a conversion efficiency of 23.0%. These results show that PVD by sputtering is an attractive and reliable technology for fabricating high performance silicon solar cells.

In this letter, we report on accurate comparative measurements of Raman scattering from bulk crystalline Si and from hydrogenated amorphous Si thin films before and after their pulse laser annealing, performed for the purpose of Si crystalline grain formation. Being accompanied by the respective optical transmittance/reflectance measurements, these data allowed us to estimate the integrated Raman scattering cross section ratios of crystalline and microcrystalline Si to hydrogenated amorphous Si and to compare the results with those known from the literature. For crystalline Si, the obtained ratio is equal to 0.75, while for microcrystalline Si, it is equal to at least 2. Our results are found to contradict the proposed earlier exponential decay dependence of the integrated Raman scattering cross section ratio of microcrystalline to amorphous Si on the crystalline grain size. The physical reasons, which support our findings, are discussed.

Insight in the thermal degradation phenomena and the relation to phase transformation is presented for cobalt disilicide (CoSi2) on narrow polysilicon lines (linewidth ranging from 30nmto1μm) using electrical and morphological analysis in the temperature range 650–900°C. When polysilicon lines are scaled laterally to 30nm, an abrupt CoSi2 sheet resistance increase (>1000Ω∕sq) is observed, which is attributed to silicide agglomeration. At localized positions along the 30-nm Co-silicided lines, Si/silicide layer inversion is observed. At low formation temperature (650°C), no agglomeration phenomena occur, but incidentally the transition from CoSi into CoSi2 is delayed on the 30-nm-wide polysilicon structures to such an extent that the CoSi2 growth virtually stops. Only using nitrogen implantation through CoSi and a CoSi2 formation temperature of 900°C, low sheet resistance values are obtained for 35-nm-wide polysilicon lines. Based on the results obtained in the present work, we propose that the abrupt incr...

Stress and defects in polycrystalline silicon (poly-Si) for thin-film transistor (TFT) were investigated on the aspect of difference of techniques between excimer laser annealing (ELA) with extremely short pulse duration and continuous-wave laser lateral crystallization (CLC). Micro-Raman spectroscopy was used for characterization. Mapping measurements with high spatial resolution were carried out for the optical-phonon mode at ∼520 cm−1 to observe distribution of stress and defects. Defects were characterized also by local-vibration modes (LVMs) in ∼2000 cm−1 region, where LVMs were induced by terminating dangling bonds at defects with hydrogen atoms. Significant tensile stress was found for both ELA and CLC, which magnitude is dominated by the thermal stress. The stress in ELA poly-Si tends to relax in the vicinity of grain boundaries. Densities of defects in grains and dangling bonds at grain boundaries in CLC poly-Si films were apparently smaller than those in ELA films. Those differences are attribut...

Electrical and structural properties of polycrystalline silicon germanium (poly-SiGe) films fabricated by pulsed-laser annealing were investigated. Observation of laser-induced melt-regrowth of SiGe films using transient conductance measurement revealed that the melt depth and the crystallization velocity increased as Ge concentration increased. The increase of the crystallization velocity resulted in increase of the average size of crystalline grains from 66 to 120 nm at the laser energy density of 360 mJ/cm2 with increasing Ge concentration from 0 to 60%. The crystalline volume ratio obtained by reflectivity spectra in the ultraviolet region also increased from 0.83 to 1.0. Numerical analysis revealed that the density of electrically active defects decreased from 3.5×1018 to 1.1×1018 cm−3 as Ge concentration increased from 0 to 80%. The density of defect states of Si0.8Ge0.2 films were reduced from 3.5×1018 to 1.9×1018 cm−3 by 13.56-MHz hydrogen plasma treatment at 250 °C, 30 W, and 130 Pa for 30 s. How...

This work examines the effects of grain boundaries on the performance and hot-carrier reliability of excimer-laser-annealed polycrystalline silicon thin film transistors (poly-Si TFTs) before and after NH3 plasma treatment. Self-aligned poly-Si TFTs, whose channel regions include a 150 nm thick laser-crystallized poly-Si layer with small grains and a 100 nm thick layer with large grains, are fabricated. Other TFTs, with large grains throughout their channels, are fabricated nearby for comparison. The trapping of electrons at grain boundaries in the drain junction creates strong local electric fields that boost the leakage current, cause the threshold voltage to decline as the drain bias increases, enhance the kink effect in the output characteristics, and degrade the hot-carrier reliability of devices. When static hot-carrier stress is applied to nonhydrogenated poly-Si TFTs for less than 104 s at VGS=10 V and VDS=20 V, hot holes are injected into the gate oxide at the same time trap states are created in...

We report on the fabrication of nanometer-scale mass sensors with subattogram sensitivity. Surface micromachined polycrystalline silicon and silicon nitride nanomechanical oscillators were used to detect the presence of well-defined mass loading. Controlled deposition of thiolate self-assembled monolayers on lithographically defined gold dots were used for calibrated mass loading. We used a dinitrophenyl poly(ethylene glycol) undecanthiol-based molecule (DNP-PEG4-C11thiol) as a model ligand for this study. Due to the fact that the gold mass is attached at the distance l0 from the end x=l of the cantilever beam, an additional moment evolves in the boundary condition of the oscillator, which was taken into consideration through the rotational inertia of the attached mass. We showed that the corresponding correction of the frequency is on the order of γ(l0/l), where γ is the attached mass normalized to the mass of the beam. The rotational inertia correction to the frequency is on the order of γ(l0/l)2. The a...

The thermal contact conductance G for polycrystalline silicon cantilever beams that are adhered to an underlying substrate is examined using two different optical techniques. Using time-domain thermoreflectance, we measure G=9±2 MW m−2 K−1 at 25 °C and G=4±1 MW m−2 K−1 at 150 °C. The room temperature value is confirmed using a modified Angstrom method, which establishes a lower limit of G>5 MW m−2 K−1. This contact conductance is a factor of 10–105 greater than values reported for metal–metal and ceramic–ceramic interfaces. The large interfacial conductance is consistent with the presence of a thin layer of water trapped between the cantilever and the substrate. The thermal conductivity Λ of the phosphorus doped polysilicon cantilever is nearly isotropic with Λcross plane=65 W m−1 K−1, and Λin plane=70 W m−1 K−1 at room temperature.

Thermally driven transport and exchange of hydrogen and deuterium in silicon-based metal-oxide-semiconductor (MOS) device-related structures were experimentally investigated using elastic recoil detection analysis. The samples were planar stacks of different materials on crystalline silicon. The materials studied included silicon oxide prepared by thermal growth, polycrystalline silicon silicon nitride, silicon oxynitride, and borophosphosilicate glass (BPSG) prepared by chemical vapor deposition (CVD). CVD was performed using either standard (hydrogen-containing) or deuterated precursors. Thermal annealing was carried out at 350–800 °C for 10–300 min in argon or in forming gas, either standard (90 vol. % N2,10 vol. % H2) or deuterated. All materials except silicon nitride were permeable to hydrogen and deuterium in the temperature range studied. Isotope exchange in the polycrystalline Si/SiO2 structure was observed above 450 °C. BPSG showed very little relative isotope exchange. Implications to MOS device processing are discussed.

Crystalline orientations of disklike grains in polycrystalline silicon (poly-Si) formed by silicide-mediated crystallization (SMC) of amorphous silicon (a-Si) have been studied and compared with those of needlelike crystallites. The disklike grain can be obtained by SMC of a-Si with a silicon–nitride cap on it and its size is as large as 42 μm by using the average Ni area density of 2.43×1014 cm−2 on the cap. On the other hand, the poly-Si crystallized without the cap layer is composed of needlelike crystallites. The electron diffraction (ED) patterns of transmission electron microscope (TEM) remain unchanged for the selected area from 1 to 10 μm diameter inside of the disklike grain, but the ED patterns of SMC poly-Si composed of needlelike crystallites show a ring pattern for the area of 10 μm diameter due to many crystalline orientations. Electron backscattered diffraction and TEM analysis indicate that each disk-like grain has a single orientation, but its orientation is not always the same as that of...

The effect of preamorphization using silicon (Si) ion, different annealing temperatures and heating rates on nucleation density and grain size of C49 and C54–TiSi2 have been studied. The average grain size of C54–TiSi2 is found to decrease when the peak annealing temperature is changed from 700 to 850 °C. We found that the nucleation threshold temperature is about 900 °C at which the C54–TiSi2 grain size levels off at about 23 nm. We also found that the grain size of C54–TiSi2 is independent of different heating rates. Our results also show that preamorphization is not so effective in reducing the C54–TiSi2 grains when annealing temperature is raised to above 850 °C. However, preamorphization does improve the grain size uniformity. By optimizing the processing parameters such as peak annealing temperature, heating rates and preamorphization, we have demonstrated the formation of C54–TiSi2 on 0.12 μm polycrystalline silicon (polysilicon) lines with no agglomeration.

A closed form, analytical expression for the interdependence of the effective diffusion length Leff and the open-circuit voltage of solar cells is derived for the parallel connection of recombination in the space-charge region and in the neutral base region. This expression allows for the calculation of Leff from the open-circuit voltage, the short-circuit current, and the base doping of the solar cell as the only quantities that need to be determined experimentally. Values of Leff calculated with our method match with an accuracy of 35% values that are determined experimentally by quantum-efficiency measurements of silicon solar cells. The agreement holds in a range 0.3 μm

The characteristics and reliability of laser-activated polycrystalline silicon thin-film transistors (poly-Si TFTs) under the stress condition of drain voltage (Vd)=12 V and gate voltage (Vg)=15 V have been investigated. In spite of reducing the source/drain resistivity by using laser activation method, the leakage current (Vg

Nanostructures of n-type amorphous silicon (a-Si) and polycrystalline silicon (poly-Si) with a height of 270 nm and line widths of 110-165 nm were fabricated directly onto a substrate through a simple imprinting process that does not require vacuum conditions or photolithography. The n-type Liquid-Si ink was synthesized via photopolymerization of cyclopentasilane (Si5H10) and white phosphorus (P4). By raising the temperature from 160 °C to 200 °C during the nanoimprinting process, well-defined angular patterns were fabricated without any cracking, peeling, or deflections. After the nanoimprinting process, a-Si was produced by heating the nanostructures at 400°C-700 °C, and poly-Si was produced by heating at 800 °C. The dopant P diffuses uniformly in the Si films, and its concentration can be controlled by varying the concentration of P4 in the ink. The specific resistance of the n-type poly-Si pattern was 7.0 × 10−3Ω ⋅ cm, which is comparable to the specific resistance of flat n-type poly-Si films.

The effect of the SiO2/polycrystalline silicon (polysilicon) interface roughness on the stability of n-channel large grain polysilicon thin-film transistors (TFTs) is investigated. The positive gate voltage of 20 V is used in the bias stress experiments, with the source and drain grounded. It is shown that the current through the gate oxide and the stability of the TFT are directly related to the importance of the interface roughness. The evolution of the TFT parameters with stress duration indicates that the turn-on voltage Von and the subthreshold swing voltage S are degraded due to the generation of dangling bond midgap states, while the leakage current IL and the maximum transconductance Gm are degraded due to the generation of strain-bond tail states. Moreover, the parameters Von and IL are found to degrade faster than the parameters S and Gm, respectively, due to electron trapping in the gate oxide.

We assess a broad range of published experiments to show that the density of states (DOS) at high-energy grain boundaries in silicon is appropriately described by the defect-pool model. This implies that the DOS of such grain boundaries depends strongly on the dopant density and on the position of the Fermi level during device processing. However, since high-energy grain boundaries consist of an amorphous layer that is confined to a width of a few angstroms, the DOS is “frozen in” after material processing and does not suffer the strong degradation effects commonly observed in bulk a-Si:H. By combining three-dimensional device modeling and the defect-pool model, we reproduce various test structures and polycrystalline thin-film Si solar cells considerably more precisely than in the past. Our simulation model potentially provides a link between processing conditions and grain boundary quality.

Unique polycrystalline silicon (poly-Si) thin films, which were permeable to a concentrated hydrofluoric acid solution through their porous grain boundaries, were investigated to elucidate the formation mechanism of their microstructure. 0.1-μm-thick permeable poly-Si thin films were made through processes of amorphous silicon film formation by low pressure chemical vapor deposition, successive postannealing for crystallization, and excess phosphorus diffusion by a phosphorus oxichloride predeposition. At the grain boundaries, porous microstructures were formed after the films were cleaned in an SC1 solution (a 1:1:5 mixture of NH4OH:H2O2:H2O at 80 °C for 10 min), whereas segregated soluble precipitates observed by a field emission secondary electron microscope were present before the SC1 cleaning. Auger electron microscope revealed that the surface of the precipitates mainly consist of silicon (∼80 at. %) and oxygen (∼20 at. %). As a result of transmission electron microscope observation, it is concluded...

To study the mobility and lifetime of charge carriers in thin film polycrystalline silicon deposited by hot-wire chemical vapor deposition, time-resolved microwave conductivity measurements have been performed. Using this technique the change in conductivity in the polycrystalline silicon films after pulsed excitation can be monitored on a nanosecond time scale, without the use of electrodes. Due to the different penetration depths of the laser wavelengths used (320, 500, and 690 nm) combined with illumination from different sides, the photoconductivity in different regions within the sample can be measured. Four different samples of polycrystalline silicon deposited on Corning glass have been studied: Poly1 (highly defective), Poly2 (device quality) and profiled layers of Poly1 and Poly2. For front or back illumination, the conductivity transients for the Poly1 film are very similar and show that lifetimes of the charge carriers generated are less than 1 ns. For the Poly2 film the mobility in the interfa...

Polycrystalline silicon layers are prepared by interference laser crystallization (ILC) in the superlateral growth regime. To characterize their microscopic photoelectrical properties, light beam induced current (LBIC) is used, employing a focused laser beam for local generation of photocarriers in the layers with spatial resolution of ≈0.4 μm. The results are correlated with surface morphology obtained by atomic force microscopy. In the single pulse ILC, the temperature profiles are optimized by changing the proportion of interfering beam intensities. The typical grains are of triangular shape, with a length of 1.5 μm and width

A method for evaluating localized grain boundary (GB) trap states in polycrystalline–silicon thin-film transistors (poly-Si TFTs) is proposed. Field effects in poly-Si TFTs are analyzed by decomposition of the two-dimensional Poisson’s equation. This analysis gives the theoretical basis for evaluating the localized GB trap state density. The trap states are evaluated with the GB barrier potential given by the activation energy of the effective mobility and with the surface potential calculated from the capacitance–voltage characteristics in poly-Si TFTs. This evaluating method was applied to several different types of poly-Si TFTs fabricated with excimer laser annealing crystallization processes. This method has succeeded experimentally in eliminating the error effects related to oxide–semiconductor interface trap states and in clarifying that the GB barrier potential has a peak in its gate bias dependence. This method has also elucidated that the GB trap state density has almost the same value independent of the grain size when the hydrogenation efficiency in poly-Si is in the same level between TFTs. The good agreement of the simulated and the measured drain currents confirm the validity of this method.

We have developed a three-dimensional numerical model of grain boundaries to simulate the electrical properties of polycrystalline silicon with doping densities larger than approximately 5×1017 cm−3. We show that three-dimensional effects play an important role in quantifying the minority-carrier properties of polycrystalline silicon. Our simulations reproduce the open-circuit voltage of a wide range of published experiments on thin-film silicon p-n junction solar cells, choosing a velocity parameter for recombination at the grain boundaries, S, in the order of 105–106 cm/s. The simulations indicate that, although S has been reduced by one order of magnitude over the last two decades, improvements in the open-circuit voltage have mainly been achieved by increasing the grain size. A few options are proposed to further reduce S.

We investigate the microstructure of polycrystalline silicon films (grain size, orientation distribution, and grain boundary population). These films are produced by laser crystallization of amorphous silicon on glass substrates by a frequency doubled Nd:YVO4 laser operating at a wavelength of 532 nm. Transmission electron microscopy reveals that the grains have an average width between 0.25 and 5 μm depending on the crystallization parameters and a length of several 10 μm. Electron backscattering diffraction experiments show that the grain orientation of the poly-Si films is textured. Type and extent of texture depend in a complex way on the thickness of the crystallized amorphous silicon layer, on the repetition rate of the laser pulses, and on whether or not an additional buffer layer is present on the glass substrate. In any case, the grain boundary population is dominated by first and second order twin boundaries.

Trap states at the oxide-silicon interface and grain boundary in laser-crystallized polycrystalline-silicon thin-film transistors were extracted. The oxide-silicon interface traps and grain boundary traps can be extracted using the low-frequency capacitance–voltage characteristic and current–voltage characteristic, respectively. The traps above and below the midgap can be extracted using n-type and p-type transistors, respectively. The oxide-silicon interface traps consist of deep states and therefore seem to be caused by dangling bonds. The grain boundary traps consist of tail states and therefore seem to be caused by distortion of silicon-silicon bonds. Moreover, degradation by self-heating was analyzed. The oxide-silicon interface traps increase after the degradation. This means that silicon-hydrogen bonds are dissolved, and dangling bonds are generated. The grain boundary traps also increase a little.

Hydrogenated amorphous silicon (a-Si:H) films on molybdenum coated glass substrates were crystallized using a XeCl excimer laser. Structural information on the resulting polycrystalline silicon (poly-Si) films was obtained from scanning electron microscopy and electron backscattering diffraction measurements. The average grain size varies with laser fluence. The maximum average grain size in the super lateral growth energy–density range is considerably smaller for poly-Si on Mo coated substrates than for poly-Si on quartz. In addition, the metal layer affects the laser fluence necessary to achieve super lateral growth. Samples crystallized under super lateral growth conditions show a preferential surface orientation along the {111} direction. Intermixing of Mo and silicon is not observed.

The solid-phase crystallization of an amorphous silicon film to polycrystalline silicon by a low-temperature (⩽600 °C) furnace anneal has been investigated in a suspended cantilever structure without underlying silicon oxide by transmission electron microscopy and Raman spectroscopy. The grain size of polysilicon increases up to ∼3.0 μm and the density of intragranular defects decreases one order of magnitude in the samples without underlying oxide, compared with those with underlying oxide. The main reasons for the high quality of the suspended structures are thought to be due to the lower stress in the films during crystallization and a reduced grain nucleation rate.

The oxide growth of rf sputtered polycrystalline Si1−xGex films was found not sensitive to the Ge concentration in the films. The infrared results showed that the oxide grown on Si0.61Ge0.39 film mainly contained GeO2 and the oxide contained Ge–O–Ge and Si–O–Ge bonds when grown on Si0.73Ge0.27 film. X-ray photoelectron spectroscopy results showed the absence of Ge in the bulk of the oxides for Si1−xGex films with x

The thickness and dopant dependence of nickel-based, metal-induced laterally crystallized (MILC) polycrystalline silicon has been systematically studied. With decreasing thickness of the starting amorphous silicon films, the MILC rate decreases and the crystal morphology deteriorates with an increasing number of nickel silicide nodules trapped in the MILC region. Doping with phosphorus or arsenic and damage introduced during ion implantation are found to slow down the MILC rate and to degrade the film morphology, whereas heavy doping with boron is found to speed up the MILC rate. Possible mechanisms responsible for the observed dependence are discussed.

Passivating contacts based on thin tunneling oxides (SiOx) and n- and p-type semi-crystalline or polycrystalline silicon (poly-Si) enable high passivation quality and low contact resistivity, but the integration of these p+/n emitter and n+/n back surface field junctions into interdigitated back contact silicon solar cells poses a challenge due to high recombination at the transition region from p-type to n-type poly-Si. Here, the transition region was created in different configurations—(a) p+ and n+ poly-Si regions are in direct contact with each other (“pn-junction”), using a local overcompensation (counterdoping) as a self-aligning process, (b) undoped (intrinsic) poly-Si remains between the p+ and n+ poly-Si regions (“pin-junction”), and (c) etched trenches separate the p+ and n+ poly-Si regions (“trench”)—in order to investigate the recombination characteristics and the reverse breakdown behavior of these solar cells. Illumination- and injection-dependent quasi-steady state photoluminescence (suns-P...

The effects of various carrier scattering mechanisms on excimer-laser-crystallized polycrystalline silicon (poly-Si) thin film transistors (TFTs) fabricated using 450 °C processes on a glass substrate were studied. Good performance of a separated by ion implanted oxygen (SIMOX) metal–oxide–semiconductor field-effect transistor (MOSFET) with field-effect mobility of 670 cm2/V s and a subthreshold swing value of 0.087 V/dec was obtained using these 450 °C processes. The results showed the formation of a good silicon/silicon dioxide (SiO2) interface that is comparable to that of thermal oxide, as well as the high capability of 450 °C processes. The performance of the above SIMOX-MOSFET is superior to that of excimer-laser-crystallized poly-Si TFTs fabricated using the same 450 °C processes. This shows that poorer performance of poly-Si TFTs is caused by the poor crystalline quality of the poly-Si film. The field-effect mobility is affected little by the in-grain microdefects and surface morphology of the exc...

We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n+-Si) under positive bias ( VG) on heavily doped n-type polycrystalline silicon (n+-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n+-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO2 conduction band. Throughout the temperature range studied here, PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm. A physics based new a...

In the pursuit of ever higher conversion efficiencies for silicon photovoltaic cells, polycrystalline silicon (poly-Si) layers on thin silicon oxide films were shown to form excellent carrier-selective junctions on crystalline silicon substrates. Investigating the pinhole formation that is induced in the thermal processing of the poly-Si on oxide (POLO) junctions is essential for optimizing their electronic performance. We observe the pinholes in the oxide layer by selective etching of the underlying crystalline silicon. The originally nm-sized pinholes are thus readily detected using simple optical and scanning electron microscopy. The resulting pinhole densities are in the range of 6.6 × 106 cm−2 to 1.6 × 108 cm−2 for POLO junctions with selectivities close to S10 = 16, i.e., saturation current density J0c below 10 fA/cm2 and contact resistivity ρc below 10 mΩcm2. The measured pinhole densities agree with values deduced by a pinhole-mediated current transport model. Thus, we conclude pinhole-mediated current transport to be the dominating transport mechanism in the POLO junctions investigated here.

The effect of reactive ion etching using chlorine or fluorine-based plasmas on aluminum-induced crystallization (AIC) of silicon on fused silica glass substrates was investigated with the goal of chemically modifying the substrate surface and thereby influencing the crystallization behavior. Chlorine etching of the glass prior to AIC resulted in six times faster silicon crystallization times and smaller grain sizes than films formed on untreated substrates while fluorine etching resulted in crystallization times double than those on untreated surfaces. The differences in crystallization behavior were attributed to changes in surface chemistry and surface energy of the glass as a result of the plasma treatment as supported by X-ray photoelectron spectroscopy and contact angle measurements. The different surface treatments were then combined with optical lithography to control the location of crystallization on the substrate surface to realize the production of patterned polycrystalline silicon films from i...

Dependence of transistor characteristics on the grain-boundary location in polycrystalline silicon (poly-Si) thin-film transistors (TFTs) has been analyzed using device simulation. In the linear region, degradation is similar wherever the grain boundary is located. On the other hand, in the saturation region, degradation is less when the grain boundary is in the pinch-off region near the drain edge and degradation is similar when the grain boundary is elsewhere. Although this dependence is similar to the dependence on the trap location in single-crystal silicon transistors, the mechanism is different. This dependence in poly-Si TFTs is because the coulombic potential barrier caused by the grain boundary is lowered in the high electric field in the pinch-off region. This is a kind of Poole–Frenkel effect.

A spatially discrete grain-boundary model for characterizing polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) is developed. This model was formulated for an interface state localized at the grain boundary. Threshold voltage (Vth) variation was analyzed using the model by changing the trap density and the location and number of grain boundaries in the poly-Si channel. The Vth shifts were found to be linearly dependent on the trap density (NGB) at the grain boundary and almost independent of the boundary location. The dependence of Vth on NGB was 0.15 V per trap density of 1012 cm−2 in long-gate TFTs. Since grain formation in the poly-Si channel is not controllable (it tends to be random), the threshold-voltage shift (ΔVth) predicted by the simulation will appear as statistical fluctuation in device fabrication. Simulation of the Vth fluctuation ranges showed that ΔVth increases with a decrease in channel length and will exceed 0.2 V in TFTs with a channel length of 1 μm or less when there is ...

Carrier transport properties were investigated for polycrystalline silicon (poly-Si:H:F) films fabricated at 300 °C by 100 MHz plasma enhanced chemical vapor deposition from gaseous mixture of SiF4 and H2. Analysis of free carrier optical absorption (FCA) revealed that 1 μm thick (400) oriented phosphorus-doped poly-Si:H:F films with a carrier concentration of 5×1019 cm−3 had the average electron mobility in crystalline grains at 40 cm2/V s, while the electron mobility of the (220) oriented phosphorus-doped poly-Si:H:F films was only 12 cm2/V s. These results indicated that (400) oriented poly-Si:H:F films had excellent quality crystalline grains. Analyses of the FCA combined with Hall effect current measurements revealed that the electrical conductivity at grain boundaries of top doped films increased as the underlying film thickness increased from 0 to 280 nm for (400) oriented phosphorus-doped/undoped double layered samples, but grain boundaries still acted as large resistive regions limiting the effec...

We successfully controlled the nucleation site and direction of solidification of polycrystalline silicon films by irradiation with an excimer laser. An amorphous silicon island, including a gradually narrowing region, was formed on a quartz glass substrate. The gradually narrowing region intentionally included a necked-down area. The sidewall and top of the amorphous silicon island were covered by a thick polycrystalline silicon film. A single pulse of excimer laser irradiation from the back through the quartz glass substrate was used to melt the island. This method resulted in lateral growth from the inner region of the island toward the outer region, at the edges of the island. When the width of the necked-down area was twice the distance of the lateral growth, only one nucleus was formed in the necked-down region. Solidification from the nucleus toward the region with the narrower width then occurred in an area 2 μm wide and 3 μm long. This method enabled position-controlled formation of large grains.

Surface morphology of polycrystalline silicon prepared by excimer laser annealing has been investigated. It was found that when a thin amorphous Si film is irradiated by excimer laser, pillars are formed on the surface of the crystallized polysilicon. To find out the mechanism, various preparation parameters such as laser power densities, shot numbers and the thickness of the amorphous Si have been studied. Several intermediate patterns have been found which illustrate the sequential formation of pillars. A surface tension model is proposed to explain these patterns. This mechanism can be applied to prepare the self-assembled silicon quantum dots, whose average size and height are 14.2 and 3.7 nm, respectively.

The instability of n-channel hydrogenated polycrystalline silicon thin-film transistors has been investigated with respect to gate biasing. The hydrogenation was performed by hydrogen ion implantation through the gate oxide. The conduction mechanism in the gate oxide was studied for positive and negative gate bias, showing that the electron tunneling is much higher for positive gate bias. The oxide conduction follows the Fowler–Nordheim (FN) tunneling mechanism for electron tunneling from the channel and Poole–Frenkel for electron tunneling from the gate polysilicon. After constant FN stressing for short duration (

The influence of the material quality and thickness on the leakage current of polycrystalline silicon thin-film transistors is investigated. Improvement of the polycrystalline silicon layer (i.e., increase of the average grain size or decrease of the intragrain defect density) reduces only the leakage current at low electric fields in the drain region. At high electric fields, the leakage current is independent of the film quality and thickness due to the fundamental nature of the leakage current mechanisms. The experimental data indicate that Poole–Frenkel enhanced emission from traps at low electric fields and band-to-band tunneling at high electric fields are the dominant conduction mechanisms of the leakage current.

A nonselective epitaxial growth process for heterojunction bipolar transistors has been studied. The difference in growth rates for epitaxial and polycrystalline films could be used to monitor the ...