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Creating high-quality, low-resistance contacts is essential for the development of electronic applications using two-dimensional (2D) layered materials. Many previously reported methods for lowering the contact resistance rely on volatile chemistry that either oxidize or degrade in ambient air. Nearly all reported efforts have been conducted on only a few devices with mechanically exfoliated flakes which is not amenable to large scale manufacturing. In this work, Schottky barrier heights of metal-MoS2 contacts to devices fabricated from CVD synthesized MoS2 films were reduced by inserting a thin tunneling Ta2O5 layer between MoS2 and metal contacts. Schottky barrier height reductions directly correlate with exponential reductions in contact resistance. Over two hundred devices were tested and contact resistances extracted for large scale statistical analysis. As compared to metal-MoS2 Schottky contacts without an insulator layer, the specific contact resistivity has been lowered by up to 3 orders of magnitude and current values increased by 2 orders of magnitude over large area (>4 cm²) films. [ABSTRACT FROM AUTHOR]

Memristive technology has been rapidly emerging as a potential alternative to traditional CMOS technology, which is facing fundamental limitations in its development. Since oxide-based resistive switches were demonstrated as memristors in 2008, memristive devices have garnered significant attention due to their biomimetic memory properties, which promise to significantly improve power consumption in computing applications. Here, we provide a comprehensive overview of recent advances in memristive technology, including memristive devices, theory, algorithms, architectures, and systems. In addition, we discuss research directions for various applications of memristive technology including hardware accelerators for artificial intelligence, in-sensor computing, and probabilistic computing. Finally, we provide a forward-looking perspective on the future of memristive technology, outlining the challenges and opportunities for further research and innovation in this field. By providing an up-to-date overview of the state-of-the-art in memristive technology, this review aims to inform and inspire further research in this field.

Scaling of monolayer transition metal dichalcogenide (TMD) field-effect transistors (FETs) is an important step toward evaluating the application space of TMD materials. Although some work on ultrashort channel monolayer (ML) TMD FETs has been published, there exist no comprehensive studies that assess their performance in a statistically relevant manner, providing critical insights into the impact of the device geometry. Part of the reason for the absence of such a study is the substantial variability of TMD devices when processes are not carefully controlled. In this work, we show a statistical study of ultrashort channel double-gated ML WS 2 FETs exhibiting excellent device performance and limited device-to-device variations. From a detailed analysis of cross-sectional scanning transmission electron microscopy (STEM) images and careful technology computer aided design (TCAD) simulations, we evaluated, in particular, an unexpected deterioration of the subthreshold characteristics for our shortest devices. Two potential candidates for the observed behavior were identified, i.e., buckling of the TMD on the substrate and loss of gate control due to the source geometry and the high- k dielectric between the metal gate and the metal source electrode.

Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS 2 films at 560 °C in 50 min, within the 450-to-600 °C, 2 h thermal budget window required for back-end-of-the-line compatibility with modern silicon technology. Transistor measurements reveal on-state current up to ∼140 μA/μm at 1 V drain-to-source voltage for 100 nm channel lengths, the highest reported to date for 1L MoS 2 grown below 600 °C using solid-source precursors. The effective mobility from transfer length method test structures is 29 ± 5 cm 2 V -1 s -1 at 6.1 × 10 12 cm -2 electron density, which is comparable to mobilities reported from films grown at higher temperatures. The results of this work provide a path toward the realization of high-quality, thermal-budget-compatible 2D semiconductors for heterogeneous integration with silicon manufacturing.

Vanadium dioxide (VO 2 ) has been widely studied for its rich physics and potential applications, undergoing a prominent insulator-metal transition (IMT) near room temperature. The transition mechanism remains highly debated, and little is known about the IMT at nanoscale dimensions. To shed light on this problem, here we use ∼1 nm-wide carbon nanotube (CNT) heaters to trigger the IMT in VO 2 . Single metallic CNTs switch the adjacent VO 2 at less than half the voltage and power required by control devices without a CNT, with switching power as low as ∼85 μW at 300 nm device lengths. We also obtain potential and temperature maps of devices during operation using Kelvin probe microscopy and scanning thermal microscopy. Comparing these with three-dimensional electrothermal simulations, we find that the local heating of the VO 2 by the CNT plays a key role in the IMT. These results demonstrate the ability to trigger IMT in VO 2 using nanoscale heaters and highlight the significance of thermal engineering to improve device behavior.

The recent surge of interest in brain-inspired computing and power-efficient electronics has dramatically bolstered development of computation and communication using neuron-like spiking signals. Devices that can produce rapid and energy-efficient spiking could significantly advance these applications. Here we demonstrate direct current or voltage-driven periodic spiking with sub-20 ns pulse widths from a single device composed of a thin VO 2 film with a metallic carbon nanotube as a nanoscale heater, without using an external capacitor. Compared with VO 2 -only devices, adding the nanotube heater dramatically decreases the transient duration and pulse energy, and increases the spiking frequency, by up to 3 orders of magnitude. This is caused by heating and cooling of the VO 2 across its insulator-metal transition being localized to a nanoscale conduction channel in an otherwise bulk medium. This result provides an important component of energy-efficient neuromorphic computing systems and a lithography-free technique for energy-scaling of electronic devices that operate via bulk mechanisms.

We investigate the valley Hall effect (VHE) in monolayer WSe 2 field-effect transistors using optical Kerr rotation measurements at 20 K. While studies of the VHE have so far focused on n -doped MoS 2 , we observe the VHE in WSe 2 in both the n - and p -doping regimes. Hole doping enables access to the large spin-splitting of the valence band of this material. The Kerr rotation measurements probe the spatial distribution of the valley carrier imbalance induced by the VHE. Under current flow, we observe distinct spin-valley polarization along the edges of the transistor channel. From analysis of the magnitude of the Kerr rotation, we infer a spin-valley density of 44 spins/μm, integrated over the edge region in the p -doped regime. Assuming a spin diffusion length less than 0.1 μm, this corresponds to a spin-valley polarization of the holes exceeding 1%.

Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption.

Selective extraction of semiconducting carbon nanotubes is a key step in the production of high-performance, solution-processed electronics. Here, we describe the ability of a supramolecular sorting polymer to selectively disperse semiconducting carbon nanotubes from five commercial sources with diameters ranging from 0.7 to 2.2 nm. The sorting purity of the largest-diameter nanotubes (1.4 to 2.2 nm; from Tuball) was confirmed by short channel measurements to be 97.5%. Removing the sorting polymer by acid-induced disassembly increased the transistor mobility by 94 and 24% for medium-diameter and large-diameter carbon nanotubes, respectively. Among the tested single-walled nanotube sources, the highest transistor performance of 61 cm 2 /V·s and on/off ratio >10 4 were realized with arc discharge carbon nanotubes with a diameter range from 1.2 to 1.7 nm. The length and quality of nanotubes sorted from different sources is compared using measurements from atomic force microscopy and Raman spectroscopy. The transistor mobility is found to correlate with the G/D ratio extracted from the Raman spectra.

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.

Conducting bridge random access memory (CBRAM) is one of the most promising candidates for future nonvolatile memories. It is important to understand the scalability and retention of CBRAM cells to realize better memory performance. Here, we directly observe the switching dynamics of Cu tip/SiO 2 /W cells with various active electrode sizes using in situ transmission electron microscopy. Conducting filaments (CFs) grow from the active electrode (Cu tip) to inert electrode (W) during the SET operations. The size of the Cu tip affects the electric-field distribution, the amount of the cation injection into electrolyte, and the dimension of the CF. This study provides helpful understanding on the relationship between power consumption and retention of CBRAM cells. We also construct a theoretical model to explain the electrode-size-dependent CF growth in SET operations, showing good agreement with our experimental results.

In this work, we developed a simple method to fabricate 12 × 4 mm 2 large scale nanostructure arrays and investigated the feasibility of indium nanodot (ND) array with different diameters and periods for refractive index sensing. Absorption resonances at multiple wavelengths from the visible to the near-infrared range were observed for various incident angles in a variety of media. Engineering the ND array with a centered square lattice, we successfully enhanced the sensitivity by 60% and improved the figure of merit (FOM) by 190%. The evolution of the resonance dips in the reflection spectra, of square lattice and centered square lattice, from air to water, matches well with the results of Lumerical FDTD simulation. The improvement of sensitivity is due to the enhancement of local electromagnetic field (E-field) near the NDs with centered square lattice, as revealed by E-field simulation at resonance wavelengths. The E-field is enhanced due to coupling between the two square ND arrays with [Formula: see text]x period at phase matching. This work illustrates an effective way to engineer and fabricate a refractive index sensor at a large scale. This is the first experimental demonstration of poor-metal (indium) nanostructure array for refractive index sensing. It also demonstrates a centered square lattice for higher sensitivity and as a better basic platform for more complex sensor designs.

Mechanical exfoliation from bulk layered crystal is widely used for preparing two-dimensional (2D) layered materials, which involves not only out-of-plane interlayer cleavage but also in-plane fracture. Through a statistical analysis on the exfoliated 2D flakes, we reveal the in-plane cleavage behaviors of six representative layered materials, including graphene, h-BN, 2H phase MoS2, 1T phase PtS2, FePS3, and black phosphorus. In addition to the well-known interlayer cleavage, these 2D layered materials show a distinctive tendency to fracture along certain in-plane crystallography orientations. With theoretical modeling and analysis, these distinct in-plane cleavage behaviors can be understood as a result of the competition between the release of the elastic energy and the increase of the surface energy during the fracture process. More importantly, these in-plane cleavage behaviors provide a fast and noninvasive method using optical microscopy to identify the lattice direction of mechanical exfoliated 2D layered materials.

Two-dimensional (2D) semimetals beyond graphene have been relatively unexplored in the atomically thin limit. Here, we introduce a facile growth mechanism for semimetallic WTe2 crystals and then fabricate few-layer test structures while carefully avoiding degradation from exposure to air. Low-field electrical measurements of 80 nm to 2 μm long devices allow us to separate intrinsic and contact resistance, revealing metallic response in the thinnest encapsulated and stable WTe2 devices studied to date (3-20 layers thick). High-field electrical measurements and electrothermal modeling demonstrate that ultrathin WTe2 can carry remarkably high current density (approaching 50 MA/cm(2), higher than most common interconnect metals) despite a very low thermal conductivity (of the order ∼3 Wm(-1) K(-1)). These results suggest several pathways for air-stable technological viability of this layered semimetal.

A record high current density of 580 μA/μm is achieved for long-channel, few-layer black phosphorus transistors with scandium contacts after 400 K vacuum annealing. The annealing effectively improves the on-state current and Ion/Ioff ratio by 1 order of magnitude and the subthreshold swing by ∼2.5×, whereas Al2O3 capping significantly degrades transistor performances, resulting in 5× lower on-state current and 3× lower Ion/Ioff ratio. The influences of moisture on black phosphorus metal contacts are elucidated by analyzing the hysteresis of 3-20 nm thick black phosphorus transistors with scandium and gold contacts under different conditions: as-fabricated, after vacuum annealing, and after Al2O3 capping. The optimal black phosphorus film thickness for transistors with scandium contacts is found to be ∼10 nm. Moreover, p-type performance is shown in all transistors with scandium contacts, suggesting that the Fermi level is pinned closer to the valence band regardless of the flake thickness.

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

High-purity semiconducting single-walled carbon nanotubes (s-SWNTs) with little contamination are desired for high-performance electronic devices. Although conjugated polymer wrapping has been demonstrated as a powerful and scalable strategy for enriching s-SWNTs, this approach suffers from significant contaminations by polymer residues and high cost of conjugated polymers. Here, we present a simple but general approach using removable and recoverable conjugated polymers for separating s-SWNTs with little polymer contamination. A conjugated polymer with imine linkages was synthesized to demonstrate this concept. Moreover, the SWNTs used are without prepurifications and very low cost. The polymer exhibits strong dispersion for large-diameter s-SWNTs with high yield (23.7%) and high selectivity (99.7%). After s-SWNT separation, the polymer can be depolymerized into monomers and be cleanly removed under mild acidic conditions, yielding polymer-free s-SWNTs. The monomers can be almost quantitatively recovered to resynthesize polymer. This approach enables isolation of "clean" s-SWNTs and, at the same time, greatly lowers costs for SWNT separation.

Creating high-quality, low-resistance contacts is essential for the development of electronic applications using two-dimensional (2D) layered materials. Many previously reported methods for lowering the contact resistance rely on volatile chemistry that either oxidize or degrade in ambient air. Nearly all reported efforts have been conducted on only a few devices with mechanically exfoliated flakes which is not amenable to large scale manufacturing. In this work, Schottky barrier heights of metal-MoS2 contacts to devices fabricated from CVD synthesized MoS2 films were reduced by inserting a thin tunneling Ta2O5 layer between MoS2 and metal contacts. Schottky barrier height reductions directly correlate with exponential reductions in contact resistance. Over two hundred devices were tested and contact resistances extracted for large scale statistical analysis. As compared to metal-MoS2 Schottky contacts without an insulator layer, the specific contact resistivity has been lowered by up to 3 orders of magnitude and current values increased by 2 orders of magnitude over large area (>4 cm(2)) films.

Large-area and highly crystalline monolayer molybdenum disulfide (MoS2) with a tunable grain size was synthesized in a H2 atmosphere. The influence of introduced H2 on MoS2 growth and grain size, as well as the corresponding mechanism, was tentatively explored by controlling the H2 flow rate. The as-grown monolayer MoS2 displays excellent uniformity and high crystallinity evidenced by Raman and high-resolution transmission electron microscopy. The Raman results also give an indication that the quality of the monolayer MoS2 synthesized in a H2 atmosphere is comparable to that synthesized by using seed or mechanical exfoliation. In addition, the electronic properties and dielectric inhomogeneity of MoS2 monolayers were also detected in situ via scanning microwave microscopy, with measurements on impedance and differential capacitance (dC/dV). Back-gated field-effect transistors based on highly crystalline monolayer MoS2 shows a field-effect mobility of ∼13.07 cm2 V(-1) s(-1) and an Ion/Ioff ratio of ∼1.1×10(7), indicating that the synthesis of large-area and high-quality monolayer MoS2 with H2 is a viable method for electronic and optoelectronic applications.

Phase-change memory (PCM) is an important class of data storage, yet lowering the programming current of individual devices is known to be a significant challenge. Here we improve the energy-efficiency of PCM by placing a graphene layer at the interface between the phase-change material, Ge2Sb2Te5 (GST), and the bottom electrode (W) heater. Graphene-PCM (G-PCM) devices have ∼40% lower RESET current compared to control devices without the graphene. This is attributed to the graphene as an added interfacial thermal resistance which helps confine the generated heat inside the active PCM volume. The G-PCM achieves programming up to 10(5) cycles, and the graphene could further enhance the PCM endurance by limiting atomic migration or material segregation at the bottom electrode interface.

A different mechanism was found for Cu transport through multi-transferred single-layer graphene serving as diffusion barriers on the basis of time-dependent dielectric breakdown tests. Vertical and lateral transport of Cu dominates at different stress electric field regimes. The classic E-model was modified to project quantitatively the effectiveness of the graphene Cu diffusion barrier at low electric field based on high-field accelerated stress data. The results are compared to industry-standard Cu diffusion barrier material TaN. 3.5 Å single-layer graphene shows the mean time-to-fail comparable to 4 nm TaN, while two-time and three-time transferred single-layer graphene stacks give 2× and 3× improvements, respectively, compared to single-layer graphene at a 0.5 MV/cm electric field. The influences of graphene grain boundaries on Cu vertical transport through the graphene layers are explored, revealing that large-grain (10-15 μm) single-layer graphene gives a 2 orders of magnitude longer lifetime than small-grain (2-3 μm) graphene. As a result, it is more effective to further enhance graphene barrier reliability by improving single-layer graphene quality through increasing grain sizes or using single-crystalline graphene than just by increasing thickness through multi-transfer. These results may also be applied for graphene as barriers for other metals.

Directed self-assembly (DSA) is a promising lithography candidate for technology nodes beyond 14 nm. Researchers have shown contact hole patterning for random logic circuits using DSA with small physical templates. This paper introduces an alphabet approach that uses a minimal set of small physical templates to pattern all contacts configurations on integrated circuits. We illustrate, through experiments, a general and scalable template design strategy that links the DSA material properties to the technology node requirements.

Neuromorphic computing is an attractive computation paradigm that complements the von Neumann architecture. The salient features of neuromorphic computing are massive parallelism, adaptivity to the complex input information, and tolerance to errors. As one of the most crucial components in a neuromorphic system, the electronic synapse requires high device integration density and low-energy consumption. Oxide-based resistive switching devices have been shown to be a promising candidate to realize the functions of the synapse. However, the intrinsic variation increases significantly with the reduced spike energy due to the reduced number of oxygen vacancies in the conductive filament region. The large resistance variation may degrade the accuracy of neuromorphic computation. In this work, we develop an oxide-based electronic synapse to suppress the degradation caused by the intrinsic resistance variation. The synapse utilizes a three-dimensional vertical structure including several parallel oxide-based resistive switching devices on the same nanopillar. The fabricated three-dimensional electronic synapse exhibits the potential for low fabrication cost, high integration density, and excellent performances, such as low training energy per spike, gradual resistance transition under identical pulse training scheme, and good repeatability. A pattern recognition computation is simulated based on a well-known neuromorphic visual system to quantify the feasibility of the three-dimensional vertical structured synapse for the application of neuromorphic computation systems. The simulation results show significantly improved recognition accuracy from 65 to 90% after introducing the three-dimensional synapses.

Laser scribing is an attractive reduced graphene oxide (rGO) growth and patterning technology because the process is low-cost, time-efficient, transfer-free, and flexible. Various laser-scribed rGO (LSG) components such as capacitors, gas sensors, and strain sensors have been demonstrated. However, obstacles remain toward practical application of the technology where all the components of a system are fabricated using laser scribing. Memory components, if developed, will substantially broaden the application space of low-cost, flexible electronic systems. For the first time, a low-cost approach to fabricate resistive random access memory (ReRAM) using laser-scribed rGO as the bottom electrode is experimentally demonstrated. The one-step laser scribing technology allows transfer-free rGO synthesis directly on flexible substrates or non-flat substrates. Using this time-efficient laser-scribing technology, the patterning of a memory-array area up to 100 cm(2) can be completed in 25 min. Without requiring the photoresist coating for lithography, the surface of patterned rGO remains as clean as its pristine state. Ag/HfOx/LSG ReRAM using laser-scribing technology is fabricated in this work. Comprehensive electrical characteristics are presented including forming-free behavior, stable switching, reasonable reliability performance and potential for 2-bit storage per memory cell. The results suggest that laser-scribing technology can potentially produce more cost-effective and time-effective rGO-based circuits and systems for practical applications.

Phase change materials are widely considered for application in nonvolatile memories because of their ability to achieve phase transformation in the nanosecond time scale. However, the knowledge of fast crystallization dynamics in these materials is limited because of the lack of fast and accurate temperature control methods. In this work, we have developed an experimental methodology that enables ultrafast characterization of phase-change dynamics on a more technologically relevant melt-quenched amorphous phase using practical device structures. We have extracted the crystallization growth velocity (U) in a functional capped phase change memory (PCM) device over 8 orders of magnitude (10(-10) < U < 10(-1) m/s) spanning a wide temperature range (415 < T < 580 K). We also observed direct evidence of non-Arrhenius crystallization behavior in programmed PCM devices at very high heating rates (>10(8) K/s), which reveals the extreme fragility of Ge2Sb2Te5 in its supercooled liquid phase. Furthermore, these crystallization properties were studied as a function of device programming cycles, and the results show degradation in the cell retention properties due to elemental segregation. The above experiments are enabled by the use of an on-chip fast heater and thermometer called as microthermal stage (MTS) integrated with a vertical phase change memory (PCM) cell. The temperature at the PCM layer can be controlled up to 600 K using MTS and with a thermal time constant of 800 ns, leading to heating rates ∼10(8) K/s that are close to the typical device operating conditions during PCM programming. The MTS allows us to independently control the electrical and thermal aspects of phase transformation (inseparable in a conventional PCM cell) and extract the temperature dependence of key material properties in real PCM devices.

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.

Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale. Herein we present a novel, VLSI-compatible doping technique to fabricate n-type CNT transistors using low work-function metal oxides as gate dielectrics. Using this technique we demonstrate wafer-scale, aligned CNT transistors with yttrium oxide (Y2Ox) gate dielectrics that exhibit n-type behavior with Ion/Ioff of 10(6) and inverse subthreshold slope of 95 mV/dec. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) analyses confirm that slow (∼1 Å/s) evaporation of yttrium on the CNTs can form a smooth surface that provides excellent wetting to CNTs. Further analysis of the yttrium oxide gate dielectric using X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) techniques revealed that partially oxidized elemental yttrium content increases underneath the surface where it acts as a reducing agent on nanotubes by donating electrons that gives rise to n-type doping in CNTs. We further confirm the mechanism for this technique with other low work-function metals such as lanthanum (La), erbium (Er), and scandium (Sc) which also provide similar CNT NFET behavior after transistor fabrication. This study paves the way to exploiting a wide range of materials for an effective n-type carbon nanotube transistor for a complementary (p- and n-type) transistor technology.

The three-dimensional (3D) cross-point array architecture is attractive for future ultra-high-density nonvolatile memory application. A bit-cost-effective technology path toward the 3D integration that requires only one critical lithography step or mask for reducing the bit-cost is demonstrated in this work. A double-layer HfOx-based vertical resistive switching random access memory (RRAM) is fabricated and characterized. The HfOx thin film is deposited at the sidewall of the predefined trench by atomic layer deposition, forming a vertical memory structure. Electrode/oxide interface engineering with a TiON interfacial layer results in nonlinear I-V suitable for the selectorless array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current (<50 μA), switching speed (<100 ns), switching endurance (>10(8) cycles), read disturbance immunity (>10(9) cycles), and data retention time (>10(5) s @ 125 °C).