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In this work, we manifest that the epitaxial structure for p-GaN gate high-electron-mobility transistor is a versatile platform to develop electronics for operating in an extremely wide temperature range (X-WTR) from 2 to 675 K, with comprehensive X-WTR studies on device operation and circuit behaviors. The key enabler for the high-temperature operation is the wide bandgap that substantially suppresses the thermal excitation of the intrinsic carrier. However, for the low-temperature side, the two-dimensional electron and hole gas (2DEG and 2DHG) channels at the heterojunctions are formed by the temperature-insensitive polarization fields, which free the carriers from freezing out. The monolithically integrated GaN n-FET, p-FET, and the resultant complementary circuits are, therefore, shown to operate in X-WTR. [ABSTRACT FROM AUTHOR]

A physical insight into the capture and emission behavior of interface/oxide states in a GaN-based metal-oxide-semiconductor (MOS) structure is of great importance to understanding the threshold voltage (VTH) instability in GaN power transistors. A time-dependent VTH shift in Ni/Al2O3/AlGaN/GaN MOS-HFETs (heterojunction field-effect transistors) and a distribution of Al2O3/III-nitride interface states (Dit) were successfully characterized by constant-capacitance deep level transient spectroscopy. It is found that in situ remote plasma pretreatments in plasma-enhanced atomic-layer-deposition could suppress Dit (EC-ET > 0.4 eV) down to below 1.3 × 1012 cm−2 eV−1. Under high applied gate bias (e.g., VG > 8 V), tunnel filling of oxide states in the Al2O3 dielectric comes into play, contributing to remarkable VTH instability in the MOS-HFETs. The tunnel distance between the 2D Electron Gas (2DEG) channel and oxide states ET,ox in the Al2O3 dielectric decreases from 3.75 to 0.82 nm as VG increases from 2 to 8 V. A further increase of VG to 11 V makes the Fermi level approach ET,ox (EC − ET ∼ 1.62 eV), which may enable direct filling. High electric field induced tunnel filling of gate oxide states could be an assignable cause for VTH instability in normally-OFF III-nitride MOS-HFETs. [ABSTRACT FROM AUTHOR]

The low-temperature gate reliability of Schottky-type p-GaN gate AlGaN/GaN heterojunction field-effect transistors under forward gate voltage stress is investigated. Both temperature-accelerated and voltage-accelerated time-dependent gate breakdown stress experiments are performed. The p-GaN gate exhibits a shorter time-to-failure at a lower temperature. It is found that the time-to-failure at "use conditions" predicted by acceleration tests at high gate bias stress could be overestimated at low temperatures. Such a discrepancy stems from the distinct dominant gate leakage mechanisms at high/low gate bias stress conditions. The dominant physical mechanism of the low-temperature gate leakage current is identified to be Poole–Frenkel emission at low gate bias and Fowler–Nordheim tunneling at high bias. From the physical model, a more accurate lifetime projection can be obtained for given use conditions. [ABSTRACT FROM AUTHOR]

In this work, by using an on-chip integrated Schottky-on-heterojunction light-emitting diode (SoHLED) which is seamlessly integrated with the AlGaN/GaN high electron mobility transistor (HEMT), we studied the effect of on-chip light illumination on the de-trapping processes of electrons from both surface and bulk traps. Surface trapping was generated by applying OFF-state drain bias stress, while bulk trapping was generated by applying positive substrate bias stress. The detrapping processes of surface and/or bulk traps were monitored by measuring the recovery of dynamic on-resistance Ron and/or threshold voltage Vth of the HEMT. The results show that the recovery processes of both dynamic Ron and threshold voltage Vth of the HEMT can be accelerated by the on-chip SoH-LED light illumination, demonstrating the potentiality of on-chip hybrid opto-HEMTs to minimize the influences of traps during dynamic operation of AlGaN/GaN power HEMTs. [ABSTRACT FROM AUTHOR]