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In this work, we present a systematic study of the effect of the stoichiometry of BaTiO3 (BTO) films grown on the Ge(001) substrate by molecular-beam-epitaxy using different characterization methods relying on beam diffraction, including reflection high-energy electron diffraction (RHEED), X-ray diffraction (XRD), and selected-area electron diffraction in transmission electron microscopy. Surprisingly, over a wide range of [Ba]/[Ti] ratios, as measured by the Rutherford backscattering spectrometry, all the BTO layers exhibit the same epitaxial relationship h100iBTO(001)// 〈110〉Ge(001) with the substrate, describing a 45° lattice rotation of the BTO lattice with respect to the Ge lattice. However, varying the [Ba]/[Ti] ratio does change the diffraction behavior. From RHEED patterns, we can derive that excessive [Ba] and [Ti] generate twinning planes and a rougher surface in the non-stoichiometric BTO layers. XRD allows us to follow the evolution of the lattice constants as a function of the [Ba]/[Ti] ratio, providing an option for tuning the tetragonality of the BTO layer. In addition, we found that the intensity ratio of the 3 lowest-order Bragg peaks I(001)/ I(002), I(101)/I(002), and I(111)/I(002) derived from ω-2θ scans characteristically depend on the BTO stoichiometry. To explain the relation between observed diffraction patterns and the stoichiometry of the BTO films, we propose a model based on diffraction theory explaining how excess [Ba] or [Ti] in the layer influences the diffraction response. [ABSTRACT FROM AUTHOR]

The tunneling current through an atomic force microscopy (AFM) tip is used to evaluate the effective electrical contact area, which exists between tip and sample in contact-AFM electrical measurements. A simple procedure for the evaluation of the effective electrical contact area is described using conductive atomic force microscopy (C-AFM) in combination with a thin dielectric. We characterize the electrical contact area for coated metal and doped-diamond tips operated at low force (<200 nN) in contact mode. In both cases, we observe that only a small fraction (<10 nm2) of the physical contact (~100 nm2) is effectively contributing to the transport phenomena. Assuming this reduced area is confined to the central area of the physical contact, these results explain the sub-10 nm electrical resolution observed in C-AFM measurements. [ABSTRACT FROM AUTHOR]

Band-to-band tunneling parameters of strained indirect bandgap materials are not well-known, hampering the reliability of performance predictions of tunneling devices based on these materials. The nonlocal band-to-band tunneling model for compressively strained SiGe is calibrated based on a comparison of strained SiGe p-i-n tunneling diode measurements and doping-profile-based diode simulations. Dopant and Ge profiles of the diodes are determined by secondary ion mass spectrometry and capacitance-voltage measurements. Theoretical parameters of the band-to-band tunneling model are calculated based on strain-dependent properties such as bandgap, phonon energy, deformation-potential-based electron-phonon coupling, and hole effective masses of strained SiGe. The latter is determined with a 6-band k.p model. The calibration indicates an underestimation of the theoretical electron-phonon coupling with nearly an order of magnitude. Prospects of compressively strained SiGe tunneling transistors are made by simulations with the calibrated model. [ABSTRACT FROM AUTHOR]

Polycrystalline silicon (pc-Si) thin-films with a grain size in the range of 0.1–100 μm grown on top of inexpensive substrates are economical materials for semiconductor devices such as transistors and solar cells and attract much attention nowadays. For pc-Si, grain size enlargement is thought to be an important parameter to improve material quality and therefore device performance. Aluminum-induced crystallization (AIC) of amorphous Si in combination with epitaxial growth allows achieving large-grained pc-Si layers on nonsilicon substrates. In this work, we made pc-Si layers with variable grain sizes by changing the crystallization temperature of the AIC process in order to see if larger grains indeed result in better solar cells. Solar cells based on these layers show a performance independent of the grain size. Defect etching and electron beam induced current (EBIC) measurements showed the presence of a high density of electrically active intragrain defects. We therefore consider them as the reason for the grain size independent device performance. Besides dislocations and stacking faults, also Σ3 boundaries were electrically active as shown by combining electron backscattered diffraction with EBIC measurements. The electrical activity of the defects is probably triggered by impurity decoration. Plasma hydrogenation changed the electrical behavior of the defects, as seen by photoluminescence, but the defects were not completely passivated as shown by EBIC measurements. In order to reveal the origin of the defects, cross section transmission electron microscopy measurements were done showing that the intragrain defects are already present in the AIC seed layer and get copied into the epitaxial layer during epitaxial growth. The same types of intragrain defects were found in layers made on different substrates (alumina ceramic, glass ceramic, and oxidized silicon wafer) from which we conclude that intragrain defects are not related to the relatively rough alumina ceramic substrates often used in combination with high temperature epitaxy. Further improvement of the material quality, and hence device performance, is therefore not simply achieved by increasing the grain size, but the intragrain quality of the material also needs to be taken into account. For pc-Si layers based on AIC and epitaxial growth, the seed layer has a crucial impact on the intragrain defect formation. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) is used in applications where inorganic material layers with uniform thickness down to the nanometer range are required. For such thicknesses, the growth mode, defining how the material is arranged on the surface during the growth, is of critical importance. In this work, the growth mode of the zirconium tetrachloride/water and the trimethyl aluminum/water ALD process on hydrogen-terminated silicon was investigated by combining information on the total amount of material deposited with information on the surface fraction of the material. The total amount of material deposited was measured by Rutherford backscattering, x-ray fluorescence, and inductively coupled plasma–optical emission spectroscopy, and the surface fractions by low-energy ion scattering. Growth mode modeling was made assuming two-dimensional growth or random deposition (RD), with a “shower model” of RD recently developed for ALD. Experimental surface fractions of the ALD-grown zirconium oxide and aluminum oxide films were lower than the surface fractions calculated assuming RD, suggesting the occurrence of island growth. Island growth was confirmed with transmission electron microscopy (TEM) measurements, from which the island size and number of islands per unit surface area could also be estimated. The conclusion of island growth for the aluminum oxide deposition on hydrogen-terminated silicon contradicts earlier observations. In this work, physical aluminum oxide islands were observed in TEM after 15 ALD reaction cycles. Earlier, thicker aluminum oxide layers have been analyzed, where islands have not been observed because they have already coalesced to form a continuous film. The unreactivity of hydrogen-terminated silicon surface towards the ALD reactants, except for reactive defect areas, is proposed as the origin of island growth. Consequently, island growth can be regarded as “undesired surface-selective ALD.” [ABSTRACT FROM AUTHOR]

We report the electrical properties of 60° dislocations originating from the +1.2% lattice mismatch between an unintentionally doped, 315 nm thick Ge0.922Sn0.078 layer (58% relaxed) and the underlying Ge substrate, using deep level transient spectroscopy. The 60° dislocations are found to be split into Shockley partials, binding a stacking fault. The dislocations exhibit a band-like distribution of electronic states in the bandgap, with the highest occupied defect state at ∼EV + 0.15 eV, indicating no interaction with point defects in the dislocation's strain field. A small capture cross-section of 1.5 × 10−19 cm2 with a capture barrier of 60 meV is observed, indicating a donor-like nature of the defect-states. Thus, these dislocation-states are not the source of unintentional p-type doping in the Ge0.922Sn0.078 layer. Importantly, we show that the resolved 60° dislocation-states act as a source of leakage current by thermally generating minority electrons via the Shockley-Read-Hall mechanism. [ABSTRACT FROM AUTHOR]

The structure, crystallinity and properties of as-deposited two-dimensional (2D) transition metal dichalcogenides are determined by nucleation mechanisms in the deposition process. 2D materials grown by atomic layer deposition (ALD) in the absence of a template are polycrystalline or amorphous. Little is known about their nucleation mechanisms. Therefore, the nucleation behavior of WS2 during plasma enhanced ALD from WF6, H2 plasma and H2S at 300 °C is investigated on amorphous ALD Al2O3 starting surface and on monocrystalline, bulk sapphire. Preferential interaction of the precursors with the Al2O3 starting surface promotes fast closure of the WS2 layer. The WS2 layers are fully continuous at WS2 content corresponding to only 1.2 WS2 monolayers. On amorphous Al2O3, (0002) textured and polycrystalline WS2 layers form with grain size of 5 to 20 nm due to high nucleation density (∼1014 nuclei/cm2). The WS2 growth mode changes from 2D (layer-by-layer) growth on the initial Al2O3 surface to three-dimensional (Volmer-Weber) growth after WS2 layer closure. Further growth proceeds from both WS2 basal planes in register with the underlying WS2 grain and from or over grain boundaries of the underlying WS2 layer with different in-plane orientation. In contrast, on monocrystalline sapphire, WS2 crystal grains can locally align along a preferred in-plane orientation. Epitaxial seeding occurs locally albeit a large portion of crystals remain randomly oriented, presumably due to the low deposition temperature. The WS2 sheet resistance is 168 MΩμm, suggesting that charge transport in the WS2 layers is limited by grain boundaries. [ABSTRACT FROM AUTHOR]

Vertical InAs nanowires (NWs) grown on a Si substrate are promising building-blocks for next generation vertical gate-all-around transistor fabrication. We investigate the initial stage of InAs NW selective area epitaxy (SAE) on a patterned Si (111) substrate with a focus on the interfacial structures. The direct epitaxy of InAs NWs on a clean Si (111) surface is found to be challenging. The yield of vertical InAs NWs is low, as the SAE is accompanied by high proportions of empty holes, inclined NWs, and irregular blocks. In contrast, it is improved when the NW contains gallium, and the yield of vertical InxGa1-xAs NWs increased with higher Ga content. Meanwhile, unintentional Ga surface contamination on a patterned Si substrate induces high yield vertical InAs NW SAE, which is attributed to a GaAs-like seeding layer formed at the InAs/Si interface. The role of Ga played in the III-V NW nucleation on Si is further discussed. It stabilizes the B-polarity on a non-polar Si (111) surface and enhances the nucleation. Therefore, gallium incorporation on a Si surface is identified as an important enabler for vertical InAs NW growth. A new method for high yield (>99%) vertical InAs NW SAE on Si using an InGaAs nucleation layer is proposed based on this study. [ABSTRACT FROM AUTHOR]

The effective bandgap is a crucial design parameter of heterojunction tunneling field-effect transistors. In this letter, we demonstrate a method to measure the effective bandgap directly from the band-to-band tunneling current of a heterojunction Esaki diode, of which we only require knowledge of the electrostatic potential profile. The method is based on a characteristic exponentially increasing current with forward bias, caused by sharp energy filtering at cryogenic temperature. We apply this method experimentally to a n+In0.53Ga0.47As/pGaAs0.5Sb0.5 Esaki diode and define requirements to apply it to other heterojunctions. [ABSTRACT FROM AUTHOR]

Strontium titanate (STO) is a dielectric with a cubic perovskite type structure and of increasing interest for microelectronics, especially in the metal-insulator-metal (MIM) capacitors due to its high dielectric constant. The dielectric constant of the STO films and consequently the performance of the MIM capacitors appear to be strongly influenced by the process conditions. In this work the authors report on the influence of various thermal treatments upon the crystallinity and morphology of strontium titanate crystals. The influence of spike, laser, or rapid thermal anneals on the morphology with respect to grain size and topography of the crystalline stoichiometric STO films is studied. Also, the use of a stack containing a Sr-rich STO (62% Sr) bottom seed layer and a stoichiometric STO top layer in combination with a thermal treatment was found to affect the microstructure of the STO film. A comparison of the electrical properties for various thermal treatments has been made. [ABSTRACT FROM AUTHOR]

Dark-field holography, a new transmission electron microscopy technique for mapping strain distributions at the nanoscale, is used to characterize strained-silicon n-type transistors with a channel width of 65 nm. The strain in the channel region, which enhances electron mobilities, is engineered by recessed Si0.99C0.01 source and drain stressors. The strain distribution is measured across an array of five transistors over a total area of 1.6 μm wide. The longitudinal tensile strain reaches a maximum of 0.58%±0.02% under the gate oxide. Theoretical strain maps obtained by finite element method agree well with the experimental results. [ABSTRACT FROM AUTHOR]

The density of hafnium oxide films grown by atomic layer deposition for high-κ gate dielectric applications was investigated for films with thickness in the nanometer range. The density, measured by combining the film thickness from transmission electron microscopy with the amount of hafnium deposited from Rutherford backscattering, decreased with decreasing film thickness. The dielectric constant of hafnium oxide remained constant with decreasing film thickness, however. The main reason for the decrease in the measured density seemed not to be a decrease in the inherent material density. Instead, the relative importance of interface roughness in the density measurement increased with decreasing film thickness. [ABSTRACT FROM AUTHOR]

Earlier work [T. Clarysse et al., Mater. Sci. Eng., B 114–115, 166 (2004); T. Clarysse et al., Mater. Res. Soc. Symp. Proc. 912, 197 (2006)] has shown that only few contemporary tools are able to measure reliably (within the international technology roadmap for semiconductors specifications) sheet resistances on ultrashallow (sub-50-nm) chemical-vapor-deposited layers [T. Clarysse et al., Mater. Res. Soc. Symp. Proc. 912, 197 (2006)], especially in the presence of medium/highly doped underlying layers (representative for well/halo implants). Here the authors examine more closely the sheet resistance anomalies which have recently been observed between junction photovoltage (JPV) based tools and a micrometer-resolution four-point probe (M4PP) tool on a variety of difficult, state-of-the-art sub-32-nm complementary metal-oxide semiconductor structures (low energy and cluster implants, with/without halo, flash- and laser-based millisecond anneal). Conventional four-point probe tools fail on almost all of these samples due to excessive probe penetration, whereas in several cases variable probe spacing (using a conventional spreading resistance probe tool) [T. Clarysse et al., Mater. Sci. Eng. R. 47, 123 (2004)] still gives useful values to within about 20%–35% due to its limited probe penetration (5–10 nm at 5 g load). M4PP measurements give systematically a sensible and reproducible result. This is also the case for JPV-based sheet resistance measurements, although these appear to be prone to correct calibration procedures and are not designed for the characterization of multijunctions. Moreover, in a significant number of cases, residual damage and/or unexpected junction-leakage currents appear to induce a strong signal reduction, limiting the applicability of the JPV technique. This has been further investigated by transmission-electron microscopy, high carrier-injection photomodulated optical-reflectance, and Synopsis-Sentaurus device simulations. [ABSTRACT FROM AUTHOR]

The reaction of a Ti (8 nm) capped Co film (15 nm) with a Si[sub 3]N[sub 4] layer (150 nm) is studied after rapid thermal annealing at 660 °C for 120 s in a N[sub 2] ambient. X-ray photoelectron spectroscopy, transmission electron microscopy, electron energy-loss spectroscopy, and Auger electron spectroscopy are used to study the reaction products. Combining the results of the different analyses yields a layer stack consisting of: TiO[sub 2]/TiO/unreacted Co/(Ti,Co)[sub 2]N/Co[sub 2]Si, followed by amorphous Si[sub 3]N[sub 4]. The reaction mechanisms are discussed. Conclusions concerning the risk for degradation of nitride spacers in advanced devices are drawn. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]