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Correlation-based detection techniques are widely used in the weak periodic signal detection field. Traditionally, they are based on extracting the correlation of a weak signal from noise. Considering the impact of a weak signal on the randomness of background noise, this article takes the opposite approach and proposes a weak signal detection technique based on the Durbin–Watson (DW) test and one-bit sampling, detecting the weak signal due to the extent to which the randomness of noise is affected. The randomness of noise is analyzed through the DW test, which is a method for detecting the randomness of data sequences through first-order autocorrelation. One-bit sampling is adopted to reduce the complexity of the sampling circuit and data processing algorithm. The effectiveness of the DW test in the situation of one-bit sampling is demonstrated through simulation and analysis. Simulation results show that the proposed technique is capable of detecting weak sinusoidal and square-wave signals with a signal-to-noise ratio (SNR) above −30 dB, and the frequency or SNR of a weak signal can be further estimated based on mutual constraints. The measured results confirm the capability. In addition, the factors of coherent sampling, noise bandwidth, and comparator threshold that influence the performance of the proposed technique are simulated and discussed in detail. [ABSTRACT FROM AUTHOR]

The detection of a high repetition rate weak signal is studied in this paper. Owing to the characteristics of the signal of interest, both high speed analog-to-digital converter (ADC) and low computational complexity data processing techniques are required for high speed real-time weak signal detection. In this paper, a novel field programmable gate array (FPGA) based high speed real-time periodic weak signal detection technique is presented. Cascaded comparators outside the FPGA and cascaded flip flops in the FPGA are used to implement a one-bit ADC, which performs quantization first followed by sampling. Based on this novel design, a time-interleaved structure with several sub-channels is further proposed to significantly improve the sampling rate of the one-bit ADC, which does not require calibration for offset, gain, and sample-time mismatches between sub-channels. Each sub-channel has a long-time coherent integration structure to coherently integrate the sampled one-bit data. A full layer clearance mechanism that only operates on specific bits of the integrated sums is proposed to overcome the influence of a noise baseline drift on the weak signal detection. Compared with the traditional adaptive threshold, this mechanism has a significantly lower computational complexity. A prototype with three sub-channels performing 1.5 Gs/s sampling is implemented to verify the proposed technique. The results obtained confirm its high sampling rate and noise baseline drift tolerance in weak signal detection. [ABSTRACT FROM AUTHOR]