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Optoelectronic devices based on layered two-dimensional (2D) van der Waals (vdW) semiconductors and their heterostructures suffer from carrier scattering, trapping, and trap-assisted recombination-generation at the vdW channel/dielectric interface. In this work, we demonstrate improved photoresponse of a dielectric-free, suspended WSe2 (p)-ReS2 (n) heterostructure photodetector in comparison to an hBN dielectric-supported structure fabricated over a common local Au back gate. The dielectric-free suspension helps in eliminating optical losses at the 2D channel–dielectric interface and optical absorption loss in the dielectric itself as the metal (gold) gate aids in reflecting the incident light to enhance absorption in the 2D heterostructure. The increase in photocurrent increases with incident illumination power and is consistent over a wide range of wavelengths. Suspension of 2D layered materials, thus, paves the route for harnessing their intrinsic properties for next generation photodetection applications. [ABSTRACT FROM AUTHOR]

Thermally varying hysteretic gate operation in few-layer ReS 2 and MoS 2 back gate field effect transistors (FETs) is studied and compared for memory applications. Clockwise hysteresis at room temperature and anti-clockwise hysteresis at higher temperature (373 K for ReS 2 and 400 K for MoS 2 ) are accompanied by step-like jumps in transfer curves for both forward and reverse voltage sweeps. Hence, a step-like conductance (STC) crossover hysteresis between the transfer curves for the two sweeps is observed at high temperature. Furthermore, memory parameters such as the RESET-to-WRITE window and READ window are defined and compared for clockwise hysteresis at low temperature and STC-type hysteresis at high temperature, showing better memory performance for ReS 2 FETs as compared to MoS 2 FETs. Smaller operating temperature and voltage along with larger READ and RESET-to-WRITE windows make ReS 2 FETs a better choice for thermally aided memory applications. Finally, temperature dependent Kelvin probe force microscopy measurements show decreasing (constant) surface potential with increasing temperature for ReS 2 ( MoS 2 ). This indicates less effective intrinsic trapping at high temperature in ReS 2 , leading to earlier occurrence of STC-type hysteresis in ReS 2 FETs as compared to MoS 2 FETs with increasing temperature. [ABSTRACT FROM AUTHOR]