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In this work, we employ the substrate hot electron injection technique as a characterization tool to examine the defect creation mechanisms in high-k HfSiON gate stacks, taking advantage of the independent control over oxide field, electron fluence, and injected electron energy which the technique allows. We show that defect creation and oxide breakdown are dependent on the energy of the injected electrons and not on the oxide field. Furthermore, we show that the energy of the injected electrons governs whether the majority of the defects are created at the Si/SiO2 interface or in the bulk of the material. Results show that at operating conditions, the primary threat to device reliability from hot carrier damage is the introduction of a permanent 3D positive bias temperature instability component introduced by increased interface trap generation, even for carriers with energy slightly above that of field accelerated electrons. We also discuss the feasibility of using substrate hot electron injection as a means to accelerate time dependent dielectric breakdown measurements, thereby allowing degradation at lower oxide fields to be probed. [ABSTRACT FROM AUTHOR]

The charge trapping is studied in metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with SrBi2Ta2O9 (SBT)/Al2O3/SiO2 gate stack by high-frequency and pulsed capacitance-voltage (CV) measurements. The ferroelectric polarization is observed by high-frequency CV. Under fast gate voltage sweep in pulsed CV, the delay of electron trapping detrapping in the buffer layer induces an opposite CV hysteresis direction than that of the ferroelectric polarization. For memory programming, the hole trapping in the gate stack limits the electric field in SBT. Furthermore, the electron trapping during stress induces serious threshold voltage instability as well as erratic memory read out. All these charge trapping problems are important for the practical application and reliability of the memory with MFIS structure. [ABSTRACT FROM AUTHOR]

As the CMOS device dimensions shrink to nanometer scale, the time-dependent VTH variability (heteroskedasticity) becomes evident due to the reduced number of stochastically behaving traps in the gate oxide. Consequently, the bias temperature instability (BTI) lifetime of nanometer-sized devices can only be correctly described in the form of time- (or workload-) dependent distributions. This paper discusses a streamlined procedure to obtain BTI lifetime projections for nanometer-scaled devices from the combination of measurements of a small sample set of nanoscaled devices and several large area test devices. [ABSTRACT FROM AUTHOR]

The energy distribution of polysilicon traps is studied by means of a simple methodology based on the measurement of fast capacitance transients observed after disturbing metal/oxide/poly-Si/Si structures with positive and negative gate voltage pulses. This methodology relies on the well-known deep-level-transient spectroscopy technique. Amorphous silicon presents two defect bands at 0.31 and 0.58 eV below the conduction band whose magnitudes are significantly reduced after spike anneal. An increasing defect tail is observed toward the valance band whose magnitude can be drastically suppressed by a proper postdeposition anneal. [ABSTRACT FROM AUTHOR]

Strontium titanate (STO) is a dielectric with a cubic perovskite type structure and of increasing interest for microelectronics, especially in the metal-insulator-metal (MIM) capacitors due to its high dielectric constant. The dielectric constant of the STO films and consequently the performance of the MIM capacitors appear to be strongly influenced by the process conditions. In this work the authors report on the influence of various thermal treatments upon the crystallinity and morphology of strontium titanate crystals. The influence of spike, laser, or rapid thermal anneals on the morphology with respect to grain size and topography of the crystalline stoichiometric STO films is studied. Also, the use of a stack containing a Sr-rich STO (62% Sr) bottom seed layer and a stoichiometric STO top layer in combination with a thermal treatment was found to affect the microstructure of the STO film. A comparison of the electrical properties for various thermal treatments has been made. [ABSTRACT FROM AUTHOR]