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Ni/Al2O3/Al film was fabricated for a high performance capacitor using electrochemical etching, anodizing, and electroless-plating. The focus of this study was to form seamless and void-free Ni electrodes on Al2O3/Al with etched tunnels. The conventional deposition method of metal was limited to full-fill for the Al tunnel pits with a high aspect ratio, a depth of about 40 μm, and diameters of about 0.5-1 μm. Nevertheless, Ni filling in tunnel pits was achieved through electroless-plating for the first time, producing a seamless and void-free electrode. The authors used a polyethylene glycol solution bath to block the Pd on top of the tunnel prior to electroless-plating, which enabled the Ni to deposit preferentially at the bottom, leading to a filling from the bottom to the top. Finally, the capacitance density for the etched and Ni electroless plated films was 220 nF/cm2 while that for a film without any etch tunnel was 12.5 nF/cm2. [ABSTRACT FROM AUTHOR]

Negative bias-induced instability of amorphous hafnium indium zinc oxide (α-HIZO) thin film transistors (TFTs) was investigated at various temperatures. In order to examine temperature-induced effects, fabricated TFTs with different combinations of gate insulator and gate metal were stressed by a negative gate bias at various temperatures. As a result, it is proved that negative bias-induced hole-trapping in the gate insulators and temperature-enhanced electron injection from the gate metals occurs at the same time at all temperatures, and the instability of HIZO TFT is more affected by the dominant factor out of the two mechanisms. [ABSTRACT FROM AUTHOR]

A comprehensive study is done regarding stabilities under simultaneous stress of light and dc-bias in amorphous hafnium-indium-zinc-oxide thin film transistors. The positive threshold voltage (Vth) shift is observed after negative gate bias and light stress, and it is completely different from widely accepted phenomenon which explains that negative-bias stress results in Vth shift in the left direction by bias-induced hole-trapping. Gate current measurement is performed to explain the unusual positive Vth shift under simultaneous application of light and negative gate bias. As a result, it is clearly found that the positive Vth shift is derived from electron injection from gate electrode to gate insulator. [ABSTRACT FROM AUTHOR]