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We report on the advantages of using Graphene-Insulator-Semiconductor (GIS) instead of Metal-Insulator-Semiconductor (MIS) structures in reliable and precise photoelectric determination of the band alignment at the semiconductor-insulator interface and of the insulator band gap determination. Due to the high transparency to light of the graphene gate in GIS structures large photocurrents due to emission of both electrons and holes from the substrate and negligible photocurrents due to emission of carriers from the gate can be obtained, which allows reliable determination of barrier heights for both electrons, Ee and holes, Eh from the semiconductor substrate. Knowing the values of both Ee and Eh allows direct determination of the insulator band gap EG(I). Photoelectric measurements were made of a series of Graphene-SiO2-Si structures and an example is shown of the results obtained in sequential measurements of the same structure giving the following barrier height values: Ee = 4.34 ± 0.01 eV and Eh = 4.70 ± 0.03 eV. Based on this result and results obtained for other structures in the series we conservatively estimate the maximum uncertainty of both barrier heights estimations at ± 0.05 eV. This sets the SiO2 band gap estimation at EG(I) = 7.92 ± 0.1 eV. It is shown that widely different SiO2 band gap values were found by research groups using various determination methods. We hypothesize that these differences are due to different sensitivities of measurement methods used to the existence of the SiO2 valence band tail. [ABSTRACT FROM AUTHOR]

We present a detailed analysis of the bias-temperature instability (BTI) of single-layer graphene field-effect transistors. Both negative BTI and positive BTI can be benchmarked using models developed for Si technologies. In particular, recovery follows the universal relaxation trend and can be described using the established capture/emission time map approach. We thereby propose a general methodology for assessing the reliability of graphene/dielectric interfaces, which are essential building blocks of graphene devices. [ABSTRACT FROM AUTHOR]

In this paper, epitaxial gadolinium oxide (Gd2O3) is reviewed as a potential high-K gate dielectric, both “as deposited” by molecular beam epitaxy as well as after integration into complementary metal oxide semiconductor (CMOS) processes. The material shows promising intrinsic properties, meeting critical ITRS targets for leakage current densities even at subnanometer equivalent oxide thicknesses. These epitaxial oxides can be integrated into a CMOS platform by a “gentle” replacement gate process. While high temperature processing potentially degrades the material, a route toward thermally stable epitaxial Gd2O3 gate dielectrics is explored by carefully controlling the annealing conditions. [ABSTRACT FROM AUTHOR]

The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd2O3) and silicon oxide (SiO2) on silicon substrates are compared after annealing at temperatures up to 1000 °C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO2 layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes. [ABSTRACT FROM AUTHOR]

With the employment of ultrathin, high dielectric constant gate materials in advanced semiconductor technology, the conventional capacitance-voltage measurement technique exhibits a series of anomalies. In particular, a nonsaturating increase in the accumulation capacitance with reducing measurement frequency is frequently observed, which has not been adequately explained to our knowledge. In this article, the authors provide an explanation for this anomaly and hence set a criterion for the lower bound on measurement frequency. We then present a model which allows the easy extraction of the required parameters and apply it to an experimental set of data. [ABSTRACT FROM AUTHOR]

A triple step alignment process for UV nanoimprint lithography (UV-NIL) for the fabrication of nanoscale fin field effect transistors (FinFETs) is presented. An alignment accuracy is demonstrated between two functional layers of less than 20 nm (3σ). The electrical characterization of the FinFETs fabricated by a full NIL process demonstrates the potential of UV-NIL for future nanoelectronic devices. [ABSTRACT FROM AUTHOR]