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Gallium oxide (β-Ga2O3) is becoming a popular material for high power electronic devices due to its wide bandgap and ease of processing. In this work, β-Ga2O3 substrates received various annealing treatments before atomic layer deposition of HfO2 and subsequent fabrication of metal–oxide–semiconductor (MOS) capacitors. Annealing of β-Ga2O3 with forming gas or nitrogen produced degraded capacitance–voltage (C–V) behavior compared to a β-Ga2O3 control sample with no annealing. A sample annealed with pure oxygen had improved C–V characteristics relative to the control sample, with a higher maximum capacitance and smaller flat-band voltage shift, indicating that oxygen annealing improved the C–V behavior. X-ray photoelectron spectroscopy also suggested a reduction in the oxygen vacancy concentration after O2 annealing at 450 °C, which supports the improved C–V characteristics and indicates that O2 annealing of β-Ga2O3 may lead to better MOS device performance. [ABSTRACT FROM AUTHOR]

As β-Ga2O3 becomes a popular semiconductor material for high-power electronic devices, researchers are presenting innovative device structures and fabrication processes to achieve high performance and enhanced reliability of these devices. In many cases, these fabrication processes involve the formation of mesas, trenches, and other structures by plasma etching of β-Ga2O3 with Cl2 and/or BCl3. This paper looks at the effects of photoresist patterning and BCl3 plasma etching prior to atomic layer deposition of HfO2 dielectric to form metal–oxide–semiconductor capacitors. The β-Ga2O3/HfO2 interface is critical for controlling device characteristics such as flat-band voltage and maximum capacitance under accumulation and can be greatly affected by roughness and chemical residues. Capacitance-voltage data and atomic force microscope (AFM) scans indicate that photoresist and BCl3 residues are not adequately removed with acetone/IPA/DIW cleaning but are removed using piranha (H2O2/H2SO4) cleaning before deposition of the dielectric. [ABSTRACT FROM AUTHOR]

In this study, we report the recoverable energy density (Urec) of lead-free antiferroelectric perovskite 0.92(Bi0.54Na0.46)TiO3-0.08BaTiO3 (BNT-BT) ultrathin films deposited directly on highly boron-doped silicon (p-Si) by a pulsed laser deposition method. Two pressure values were used in the growing conditions, 4.67 × 10−5 and 13.3 Pa, at a fixed substrate temperature of 700 °C. After that, the films were subjected to postannealing under an oxidizing atmosphere at 700 °C for 1 h. A conventional lithography process was used to define vertical metal–ferroelectric–p-Si structures and evaluate the energy storage characteristics. Cross-sectional SEM images showed achieved thicknesses of about 11–13 nm. The high electric field strengths of 3.8 and 4.5 MV/cm supported for BNT-BT ultrathin films deposited at 4.67 × 10−5 and 13.3 Pa, respectively, imply a high-quality perovskite thin-film growth on p-Si. The 11-nm ultrathin film grown at 13.3 Pa showed higher Urec, efficiency (η), and a maximum applied electric field of 30 J/cm3, 83%, and 4.5 MV/cm, respectively. [ABSTRACT FROM AUTHOR]

The fin width dependence of negative bias temperature instability (NBTI) of double-gate, fin-based p-type Field Effect Transistors (FinFETs) fabricated on silicon-on-insulator (SOI) wafers was investigated. The NBTI degradation increased as the fin width narrowed. To investigate this phenomenon, simulations of pre-stress conditions were employed to determine any differences in gate oxide field, fin band bending, and electric field profile as a function of the fin width. The simulation results were similar at a given gate stress bias, regardless of the fin width, although the threshold voltage was found to increase with decreasing fin width. Thus, the NBTI fin width dependence could not be explained from the pre-stress conditions. Different physics-based degradation models were evaluated using specific fin-based device structures with different biasing schemes to ascertain an appropriate model that best explains the measured NBTI dependence. A plausible cause is an accumulation of electrons that tunnel from the gate during stress into the floating SOI fin body. As the fin narrows, the sidewall device channel moves in closer proximity to the stored electrons, thereby inducing more band bending at the fin/dielectric interface, resulting in a higher electric field and hole concentration in this region during stress, which leads to more degradation. The data obtained in this work provide direct experimental proof of the effect of electron accumulation on the threshold voltage stability in FinFETs. [ABSTRACT FROM AUTHOR]

The ferroelectric (FE) properties of 10-nm-thick Hf0.5Zr0.5O2 (HZO) films deposited by an atomic layer deposition technique were improved by adopting O3 as an oxygen source instead of H2O. All HZO films were annealed at 400 °C for 1 min in an N2 atmosphere after TiN top electrode deposition. Regardless of the oxygen source, the HZO films exhibited the formation of a noncentrosymmetric orthorhombic phase, which is responsible for FE behavior with the suppression of the monoclinic phase. However, compared to the O3-based HZO film, it was confirmed that the H2O-based HZO film was more incorporated with hydrogen derived from H2O, thereby degrading FE polarization and leakage behavior. The results indicate that the strategy of using O3 as the oxygen source is useful for the fabrication and integration of FE HZO films for next-generation memory applications. [ABSTRACT FROM AUTHOR]

In this letter, the ferroelectric (FE) properties of 5-nm-thick Hf0.5Zr0.5O2 (HZO) films deposited by atomic layer deposition have been investigated. By reducing the HZO film thickness to 5 nm, low-voltage operation (1.0 V) of the HZO-based capacitor was achieved while maintaining a remnant polarization (Pr) of about 10 μC/cm2 (i.e., 2Pr of 20 μC/cm2). Meanwhile, in order to form an orthorhombic phase, which is responsible for FE properties, a rapid thermal annealing process was performed after TiN top electrode deposition. The FE properties were realized after low temperature annealing (450 °C for 1 min), making them compatible with the back-end of the line. In addition, the low operating voltage and the suppression of an additional monoclinic phase formation by stress-induced crystallization induced a robust endurance (>1010 cycles at 1.2 V) of the 5-nm-thick HZO sample. [ABSTRACT FROM AUTHOR]

High quality sub-10 nm high-k dielectrics are deposited on top of MoS2 and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. The results show that the Al2O3 buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS2/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. Dual-gate transistors encapsulated in an Al2O3 dielectric demonstrate a near-ideal subthreshold swing of ∼60 mV/dec and a high field effect mobility of 100 cm2/V·s. [ABSTRACT FROM AUTHOR]

We report on the effect of the Hf0.5Zr0.5O2 (HZO) film thickness on the ferroelectric and dielectric properties using pulse write/read measurements. HZO films of thicknesses ranging from 5 to 20 nm were annealed at 400 °C for 1 min in a nitrogen ambient to be compatible with the back-end of the line thermal budget. As the HZO film thickness decreases, low-voltage operation (1.0 V or less) can be achieved without the dead layer effect, although switching polarization (Psw) tends to decrease due to the smaller grain size. Meanwhile, for 20-nm-thick HZO films prepared under the identical stress (similar TiN top electrode thickness and thermal budget), the Psw and dielectric constant are reduced because of additional monoclinic phase formation. [ABSTRACT FROM AUTHOR]

We report on atomic layer deposited Hf0.5Zr0.5O2 (HZO)-based capacitors which exhibit excellent ferroelectric (FE) characteristics featuring a large switching polarization (45 μC/cm2) and a low FE saturation voltage (~1.5V) as extracted from pulse write/read measurements. The large FE polarization in HZO is achieved by the formation of a non-centrosymmetric orthorhombic phase, which is enabled by the TiN top electrode (TE) having a thickness of at least 90 nm. The TiN films are deposited at room temperature and annealed at 400 ºC in an inert environment for at least 1 min in a rapid thermal annealing system. The room-temperature deposited TiN TE acts as a tensile stressor on the HZO film during the annealing process. The stress-inducing TiN TE is shown to inhibit the formation of the monoclinic phase during HZO crystallization, forming an orthorhombic phase that generates a large FE polarization, even at low process temperatures. [ABSTRACT FROM AUTHOR]

In this paper, the effect of atomic layer deposited ZrO2 gate dielectrics, deposited at low temperature (100 °C), on the characteristics of recessed-gate High Electron Mobility Transistors (HEMTs) on Al0.25Ga0.75N/GaN/Si is investigated and compared with the characteristics of those with ZrO2 films deposited at typical atomic layer deposited (ALD) process temperatures (250°C). Negligible hysteresis (ΔVth <20 mV), low gate leakage current (Ig@2V = 6.6 X 10-66A/cm2), high breakdown voltage(>4 V), and low interfacial state density (Dit = 3.69 X 1011 eV-1cm-2) were observed on recessed gate HEMTs with ~5 nm ALD-ZrO2 films grown at 100°C. The excellent properties of recessed gate HEMTs are due to the absence of an interfacial layer and an amorphous phase of the film. An interfacial layer between 250°CZrO2 and GaN is observed via highresolution transmission electron microscopy and X-ray photoelectron spectroscopy. However, 100°C-ZrO2 and GaN shows no significant interfacial layer formation. Moreover, while 100°C-ZrO2 films maintain an amorphous phase on either substrate (GaN and Si), 250°C-ZrO2 films exhibit a polycrystalline-phase when deposited on GaN and an amorphous phase when deposited on Si. Contrary to popular belief, the lowtemperature ALD process for ZrO2 results in excellent HEMT performance. [ABSTRACT FROM AUTHOR]

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ~69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias. [ABSTRACT FROM AUTHOR]

Transition metal dichalcogenides (TMDs) have attracted intensive attention due to their atomic layer-by-layer structure and moderate energy bandgap. However, top-gated transistors were only reported in a limited number of research works, especially transistors with a high-k gate dielectric that are thinner than 10 nm because high-k dielectrics are difficult to deposit on the inert surface of the sulfide-based TMDs. In this work, the authors fabricated and characterized top-gated, few-layer MoS2 transistors with an 8 nm HfO2 gate dielectric. The authors show that the cleaning effect of ultrahigh vacuum annealing before high-k deposition results in significantly reduced gate leakage current of HfO2, and they show that N2 or a forming gas anneal after device fabrication affects the threshold voltage, drive current, dielectric leakage, and C-V frequency dependence. This work demonstrates how the fabrication process can affect the yield and the electrical characterization of top-gated TMD transistors, which in effect can help researchers further enhance the performance of their devices. [ABSTRACT FROM AUTHOR]

Hot carrier injection (HCI) degradation is evaluated for n-metal oxide semiconductor (MOS) and pMOS high-κ-fin shaped field effect transistor with (100) and (110) sidewall surface orientations. It was found that impact ionization at the source, in addition to the traditional drain side enhances HCI degradation for the Vg=Vd condition. The degradation increases with decreasing fin length, with negligible dependence on substrate orientation. [ABSTRACT FROM AUTHOR]

We have investigated the physical mechanisms that result in comparable electron mobility measured from (100) and (110) sidewall double-gate fin field-effect transistors (FinFETs). Using a self-consistent Schrodinger-Poisson simulator coupled with a sp3d5s* tight-binding bandstructure, we have shown that the (100)/<100> and (110)/<110> average conductivity effective mass values are similar. This is explained by the much heavier non-parabolic confinement mass for Δ2 valley of (110) FinFETs, which leads to lower Δ2 energy than Δ4. Thus, for both (100) and (110), the majority of electrons occupy the Δ2 valley with 0.19m0 conductivity effective mass, resulting in comparable electron mobility. [ABSTRACT FROM AUTHOR]

The breakdown characteristics of the crystalline and amorphous hafnium (Hf) silicates have been studied using metal-insulator-metal capacitors. It is found that, although the distribution of time-dependent dielectric breakdown and charge to breakdown (QBD) are affected by crystallization, the breakdown is primarily controlled by the electric field rather than charge fluence. [ABSTRACT FROM AUTHOR]

A methodology to analyze charge pumping (CP) data, which allows positions of probing traps in the dielectric to be identified, was applied to extract the spatial profile of traps in SiO2/HfO2 gate stacks. The results suggest that traps accessible by CP measurements in a wide frequency range, down to few kilohertz, are located within or near the interfacial SiO2 layer rather than in the bulk of the high-k film. [ABSTRACT FROM AUTHOR]

We report measurement of fast transient charging effects (FTCE) in enhancement-mode n-channel GaAs, InP, and In0.53Ga0.47As field-effect transistors (FETs) using Al2O3 as the gate dielectric. The FTCE data reveal superior drive current and enhanced threshold voltage stability for In0.53Ga0.47As FETs. We further report charge pumping measurements for In0.53Ga0.47As transistors, revealing that the majority of interface traps are donor traps, as well as an increased trap density within the Al2O3 bulk. Such data, together with FTCE data, reveal that drain current degradation observed during pulsed I-V measurements is predominantly due to slow oxide traps, underscoring their significance within III-V/high-κ metal-oxide-semiconductor FETs. [ABSTRACT FROM AUTHOR]