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Neural Networks (NN) can be efficiently accelerated in a neuromorphic fabric based on emerging resistive non-volatile memories (NVM), such as Spin Transfer Torque Magnetic RAM (STT-MRAM). Compared to other NVM technologies, STT-MRAM offers many benefits, such as fast switching, high endurance, and CMOS process compatibility. However, due to its low ON/OFF-ratio, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed current and, in turn, degradation of inference accuracy. In this article, we analyze the impact of the sensed accumulated current variation on the inference accuracy in Binary NNs and propose a design-time reference current generation method to improve the robustness of the implemented NN under different temperature and process variation scenarios (up to 125 °C). Our proposed method is robust to both process and temperature variations. The proposed method improves the accuracy of NN inference by up to 20.51% on the MNIST, Fashion-MNIST, and CIFAR-10 benchmark datasets in the presence of process and temperature variations without additional runtime hardware overhead compared to existing solutions. [ABSTRACT FROM AUTHOR]

Recent development in neural networks (NNs) has led to their widespread use in critical and automated decision-making systems, where uncertainty estimation is essential for trustworthiness. Although conventional NNs can solve many problems accurately, they do not capture the uncertainty of the data or the model during optimization. In contrast, Bayesian neural networks (BNNs), which learn probabilistic distributions for their parameters, offer a sound theoretical framework for estimating uncertainty. However, traditional hardware implementations of BNNs are expensive in terms of computational and memory resources, as they (i) are realized with inefficient von Neumann architectures, (ii) use a significantly large number of random number generators (RNGs) to implement the distributions of BNNs, and (iii) have a substantially greater number of parameters than conventional NNs. Computing-in-memory (CiM) architectures with emerging resistive non-volatile memories (NVMs) are promising candidates for accelerating classical NNs. In particular, spintronic technology, which is distinguished by its low latency and high endurance, aligns very well with these requirements. In the specific context of Bayesian neural networks (BNNs), spintronics technologies are very valuable, thanks to their inherent potential to act as stochastic or as deterministic devices. Consequently, BNNs mapped on spintronic-based CiM architectures could be a highly efficient implementation strategy. However, the direct implementation on CiM hardware of the learned probabilistic distributions of BNN may not be feasible and can incur high overhead. In this work, we propose a new Bayesian neural network topology, named SpinBayes, that is able to perform efficient sampling during the Bayesian inference process. Moreover, a Bayesian approximation method, called in-memory approximation, is proposed that approximates the original probabilistic distributions of BNNwith a distribution that can be efficiently mapped to spintronic-based CiM architectures. Compared to state-of-the-art methods, the memory overhead is reduced by 8x and the energy consumption by 80x. Our method has been evaluated on several classification and semantic segmentation tasks and can detect up to 100% of various types of out-of-distribution data, highlighting the robustness of our approach, without any performance sacrifice. [ABSTRACT FROM AUTHOR]

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate as a universal on-chip memory technology due to its non-volatility, high density, and scalability. However, high write energy and latency are its major shortcomings, particularly for fast cache applications. High write costs can efficiently be reduced by relaxing the STT-MRAM non-volatility requirements at the expense of significant increase in retention failure and read disturb rates resulting in data corruption. Hybrid STT-MRAM architecture combining non-volatile (NVM) and semi-volatile (SVM) STT-MRAM blocks has been proposed recently, which provides energy-efficiency, high storage capacity, better performance, and high reliability. However, a key and challenging requirement is efficient data mapping and migration between NVM and SVM sub-arrays to maximize the benefits of such hybrid caches. On-the-fly data migration decisions usually depend on the last seen data behavior, as it is assumed to be identical to the next one, which has very limited accuracy for rapidly varying workload behavior. In this article, we propose a simple but effective on-the-fly data management policy, which mainly relies on the supervised learning data-pattern classification for quick and highly accurate prediction of the data behavior in the oncoming execution time. Three prediction approaches are proposed and compared for a maximum and average achieved accuracy of 86% and 75%, respectively. Our data management policies aim to optimally leverage the specific features of NVM (high reliability) and SVM blocks (fast and energy-efficient write) of hybrid STT-MRAM memory with minimal migration costs (i.e., energy and performance overheads). Our experimental evaluation reports that for a hybrid STT-MRAM cache with the proposed prediction techniques, the total energy consumption can be reduced around 10.5%, on average, in comparison to the state-of-the-art. [ABSTRACT FROM AUTHOR]

Carbon Nanotube Field Effect Transistor (CNTFET)-based technologies become more and more a concurrent alternative to Metal Oxide Semiconductor Field Effect Transistors (MOSFET) technologies. In contrast to a MOSFET technology, the active layer of a CNTFET technology is not a regular silicon film with homogeneous doping and rectangular dimensions, but an array of mostly aligned carbon nanotubes (CNTs). The quality of this active layer, which depends on various technology process parameters, is expressed by parameters such as CNT alignment and array density. These parameters affect the electrical properties of the logic cells placed on top of the active layer and hence the overall CNTFET circuit yield. Although not all parameters in CNT fabrication process can be fully controlled, designers still need to assure a very high yield of their cell layouts, that is, a high reproducibility of the electrical characteristics to achieve a reasonable manufacturing yield for the entire chip. In this work we close the gap between CNTFET process fabrication and circuit design by presenting a novel accurate model for active layers in CNTFET-based technologies. Our model enables the designers to obtain technology-dependent driver strength of the custom cell layouts under realistic conditions. The new model can also be used to extract and evaluate CNTFET Design for Manufacturing (DfM) and Design for Robustness (DfR) design rules, and provide feedback to adjust process technology parameters to achieve desirable functional yield. [ABSTRACT FROM AUTHOR]

Several emerging nano-technologies, including crossbar nano-architectures, have recently been studied as possible replacement or supplement to CMOS technology in the future. However, extreme process variation and high failure rates, mainly due to atomic device sizes, are major challenges for crossbar nanoarchitectures. This article presents variation- and defect-tolerant logic mapping on crossbar nano-architectures. Since variation/defect-aware mapping is an NP-hard problem, we introduce a set of Integer Linear Programming (ILP) formulations to effectively solve the problem in a reasonable time. The proposed ILP formulations can be used for both diode-based and FET-based crossbars. Experimental results on benchmark circuits show that our approach can reduce the critical-path delay 39% compared to the Simulated Annealing (SA) method. It can also successfully achieve 97% defect-free mapping with 40% defect density. It can tolerate process variations to meet timing constraints in 95% of the cases, compared to only 77% achieved by SA. [ABSTRACT FROM AUTHOR]

Carbon Nanotube Field Effect Transistors (CNFETs) show great promise as extensions to silicon CMOS. However, CNFET-based circuits will face great fabrication challenges that will translate into important parameter variations and decreased reliability. Hence, asynchronous logic, which is intrinsically more robust to variability, seems an ideal and perhaps unavoidable choice for digital circuits in CNFET technology. This article presents the results on the design and analysis of a CNFET-based implementation of an asynchronous circuit primitive: theMuller C-element. Using a CNFET SPICE model, we evaluate the robustness of CNFET-based C-element in the presence of CNT fabrication-related nonidealities. We investigate a quantitative evaluation of how timing variability impacts the functionality of a C-element and then, extract the necessary delay constraints of the C-element circuit from the signal transition graph specification. Considering the large degrees of spatial correlation observed between the CNFETs fabricated on directionally grown CNTs, a layout technique is exploited to overcome the robustness challenges of a CNFET-based C-element. Extensive Monte Carlo simulations on the proposed technique have demonstrated the effectiveness of the proposed CNFET-based C-element by improving approximately 50X in its robustness in expense of 65% area, 47% delay, and 56% power consumption overheads. Experimental results indicate that implementation of some CNFET-based Quasi Delay Insensitive (QDI) benchmark circuits using the proposed C-element results in significant robustness improvement with negligible power and throughput overheads. As a promising step toward CNFET-based giga-scale integrated circuits, this article shows that the asynchronous logic is an effective approach to design robust integrated circuits in CNFET technology with inherent extreme physical variations. [ABSTRACT FROM AUTHOR]

It is anticipated that the number of defects in nanoscale devices fabricated using bottom-up self-assembly process is significantly higher than that for CMOS devices fabricated by conventional top-down lithography patterning. This is mainly because of inherent lack of control in self-assembly fabrication as well as atomic scale of devices. The goal of defect tolerance, as an integral part of nano computing, is to obtain error-free computation from such fabrics containing defective elements. In this article, an application-independent defect tolerant scheme for reconfigurable crossbar array nanoarchitectures is presented. The main feature of this approach is that the existence and location of defective resources within the nano-fabric are hidden from the entire design flow, resulting in minimum post-fabrication customization per chip and minimum changes to the entire design and synthesis flow. It is also shown how to drastically minimize the area overhead associated with this flow. The proposed technique requires extraction of regular yet incomplete defect-free subsets, in contrast to previously proposed complete defect-free subsets. This can greatly reduce the area overhead required for defect tolerance while not sacrificing logic mapping or signal routing capabilities. Extensive simulation results confirm considerable reduction in the area overhead without any negative impact on the usability of modified defect-free subsets. [ABSTRACT FROM AUTHOR]

An introduction is presented in which the authors discuss various reports within the issue on topics including matrix calculus, digital circuits and integer cosine transform.