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Power line communication (PLC) technology is actually among the most renowned technologies for home environments due to their low-cost installation opportunities. In this study, the bit error rate (BER) performances of binary low-density parity check (LDPC) coded orthogonal frequencydivision multiplexing (OFDM) systems have been considered over indoor PLC channels. Performances comparison of diverse soft and hard decision LDPC decoder schemes such as Min-Sum (MS), weighted bit flipping (WBF), gradient descent bit-flip (GDBF), noisy gradient descent bit-flip (NGDBF) and its few variants including the single-bit NGDBF (S-NGDBF), multi-bit NGDBF (M-NGDBF) and smoothed-multi-bit NGDBF (SM-NGDBF) decoders were examined in the modeled network. To evaluate the BER performance analyses three different PLC channel scenarios were generated by using new and more realistic PLC channel model proposal were also employed. All of the simulations performed in Canete's PLC channel model showed that remarkable performance improvement can be achieved by using short-length LDPC codes. Especially, the improvements are striking when the MS or SM-NGDBF decoding algorithms are employed on the receiver side. [ABSTRACT FROM AUTHOR]

The improved LDPC code decoding algorithm mainly refereed to improving decoding performance or reducing the decoding computation complexity. No matter hard decision or soft decision LDPC code decoding algorithm, we can get all ring number by one test, instead of testing each long ring number, after optimizing ring detection algorithm. We putted forward the application of Gaussian Markov Random Field model to realize the source parameter estimation, and make logarithmic likelihood ratio correction of bit sequence received by the channel decoding end. Joining source residual redundancy information is to increase the decoder error correction ability. Source estimation adaptive variable can correct coefficient, and it was regulated by error rate. Under the condition that computational complexity increasedlittlely, the LDPC code decoding algorithm based on MRF effectively improved the decoding performance and implemented the improvement of LDPC code decoding algorithm. In the end, we realized the decoding algorithm by using FPGA. [ABSTRACT FROM AUTHOR]

Low Density Parity Check Code (LDPC) is a kind of linear block codes based on sparse check matrix. As a kind of channel coding, whose error performance approach Shannon limits, it has better error correction capability, more flexible structure and lower decoding complexity. Currently most of the LDPC code researches are on the premise of the AWGN channel and BSC channel, which mainly in the range of the binary LDPC codes. According to the above problem, this paper analyzes the various decoding performance of non-binary LDPC codes in Rayleigh channel, and realizes a non-binary LDPC decoder in Rayleigh channel through the FPGA design. The paper begins with an overall discussion of issues surrounding the use of non-binary LDPC codes. And then the bit-error-rate (BER) performances of different non-binary LDPC codes decoding algorithm are compared on the independent Rayleigh fading channel. Finally, this decoder design is implemented based on 5CSEMA5F31C6 FPGA (devised by Altera Company) to illustrate the concepts discussed in the paper. [ABSTRACT FROM AUTHOR]