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This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-μm CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.422/0.536 LSB and −0.721/0.758 LSB, respectively. • A 16-bit 1 Msps SAR ADC is manufactured in 0.18 μm CMOS process with 170.47 dB FoMs. • A split-ADC digital calibration scheme based on dynamic element matching can improve the SFDR effectively. • A segmented capacitor array of 4 sub-capacitor arrays decreases the total capacitance of the high-resolution SAR ADC. • A dual-mode automatic zero comparator is utilised to reduce power consumption. [ABSTRACT FROM AUTHOR]

In this paper, an area-and-energy-efficient 10-bit single-ended (SE) counter-type (CT) analog-to-digital converter (ADC) with dual 5-bit capacitive digital-to-analog converter (DAC) arrays and dual 5-bit counters is presented. The 10-bit capacitive-DAC (CDAC) array and counter of the conventional counter-type structure are divided into two 5-bit CDAC arrays and counters, respectively. Significant improvements are achieved in comparison to the conventional counter-type ADC as follows: the capacitance of the most-significant-bit (MSB) capacitor is reduced by 96.88 % from 512C to 16C; the total capacitors are reduced by 93.75 % from 1024C to 64C; the total clock cycles required in the conversion phase are reduced by 93.94 % from 1023 to 62; the average switching energy is reduced by 98.55 % from 2390CV2 to 35CV2. The proposed ADC occupies a smaller area, performs much faster, and its power consumption is greatly reduced. This structure has a simple design with small sampling capacitor (32C) and does not require a rail-to-rail comparator compared to SAR ADCs. It is suitable for biomedical and multi-channel applications. The proposed ADC is post-layout simulated in 65-nm CMOS technology which occupies 0.016 mm2 area. This ADC has 85.43 nW power consumption, 9.64 ENOB on 33.33 kS/s sampling rate, and 3.23 fJ/conversion-step FOM. [ABSTRACT FROM AUTHOR]

Abstract This paper configures a successive approximation register (SAR) analog-to-digital converter (ADC) based on a new switching algorithm with efficient energy consumption. The proposed switching algorithm applies the same reference voltage to the bottom plates of all capacitors in each capacitor array to drain no energy through capacitors. In addition to a 100% energy saving in the switched-capacitor digital-to-analog converter (DAC) block, configuration of an N -bit SAR ADC shows a 50% capacitor area reduction in comparison with the conventional SAR ADC. [ABSTRACT FROM AUTHOR]

Abstract A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (V cm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 μm technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC. [ABSTRACT FROM AUTHOR]

This paper presents a capacitor sample-hold oscillator architecture which realizes temperature-stabilized operation without a precise reference generator by using a capacitor to sample-hold the peak charge voltage of the previous phase as the reference for the current phase. Due to its dual-way charging and discharging structure, the peak charge voltage for each phase will eventually stabilized around half the supply voltage. The frequency of the oscillator depends on the RC time constants of capacitors charging (discharging) across passively-temperature-stabilized resistive elements and the comparator delay time. By analyzing the temperature characteristics of the comparator delay time and using temperature compensated bias currents to achieve temperature stabilization of the delay time, this architecture improves the overall temperature stability. This architecture has been designed and verified in 0.18-μm CMOS technology. The simulation results demonstrate this design consumes 7.99 μW from a 1.8 V supply voltage at 58.9 kHz and achieves a temperature stability of best 22.19 ppm/℃(TT Corner) from −40◦C to 90◦C, and frequency variations of ± 0.3 % for supply changes from 1.25 to 1.8 V. [ABSTRACT FROM AUTHOR]

Abstract: A compact differential flipped voltage follower (DFVF) with low power consumption, capable to deliver currents several orders of magnitude larger than its quiescent current and with large capacitive loads is presented. In the proposed circuit, a current comparator activates an auxiliary transistor whenever is required to hand over additional current and reach class-AB operation. Furthermore, Miller compensation is performed, by taking advantage of the large impedance node of the comparator it is possible to reduce forty times the compensation capacitor compared to other topologies under the same conditions. The proposed architecture is validated by post-layout simulations using the parameters of an ON SEMI, double-poly, three metal layers, CMOS technology and the Pelgrom's mismatch model. A Winner-Takes-All circuit, a median filter and a current conveyor are presented as examples of application of the proposed topology. [Copyright &y& Elsevier]

Abstract: This paper will demonstrate how signals from analog sensors can be directly interfaced to any digital embedded system even though they may not be equipped with an on-chip ADC (Analog-to-Digital Converter), comparator or OP amp (Operational Amplifier). With only two resistors and one capacitor, we will present a solution that allows analog voltages to be measured directly using only a few digital I/O-pins. The digital target system requirements are minimized and limited to only two digital I/O-pins (with tri-state capability). No ADC, comparators, timers or capture modules are necessary. The extremely modest hardware requirements make it a suitable solution also for CPLDs/FPGAs (Complex Programmable Logic devices/Field Programmable Gate Arrays). Since this solution will allow even the simplest embedded system to be interfaced to analog voltage sensors, it has the potential of reducing design costs considerably. The proposed design is for DC or low-frequency signals and compared to other similar solution, this design needs no embedded analog blocks at all. [Copyright &y& Elsevier]

Abstract: A charge-pump and comparator based technique is presented for power-efficient pipelined analog-to-digital conversion. The technique takes advantage of a passive charge pump to implement the core function of residue voltage amplification and exploits a comparator-controlled charging circuit to buffer the residue voltage to the next stage. Unlike the conventional buffer circuit using source followers, no voltage headroom is sacrificed in this voltage buffering scheme. The comparator overshoot due to comparator delay is minimized by a self-cancellation scheme. The proposed pipelined ADC technique uses only capacitors, comparators and current sources with digital calibration to achieve low power consumption. Designed and fabricated in a 0.18μm CMOS technology, a proof-of-concept ADC has measured 39.1dB SNDR (6.2-bit ENOB) at 25MS/s while consuming 3.5mW from a 1.8V supply. [Copyright &y& Elsevier]