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It is challenging to understand and predict interfacial delamination in multi-layered integrated circuit (IC) packaging due to the difficulties in experimentally quantifying the critical fracture energy of interfacial adhesion. This study takes a combined approach based on molecular dynamics (MD) simulation and finite element method (FEM) to characterize the interfacial fracture energy and predict delamination in the Cu/Ti/SiO 2 /Si multilayer systems. MD simulation is first conducted on each interface of the multiple layers at the atomistic level to obtain the material parameters such as the critical interfacial fracture energy that are required for the interfacial cohesive constitutive relation. Then, FEM is used to model and predict the interfacial delamination of the multi-layered system under indentation loading at the macroscale with the cohesive zone being considered around the delamination or crack tips. Finally, the indentation damage test is performed to validate the modeling results. The proposed combined modeling approach will have the potential to provide guidance in design and applications of IC packaging for improved stability and reliability. [ABSTRACT FROM AUTHOR]

Three-dimensional (3D) integration using the through-silicon via (TSV) approach becomes one promising technology in 3D packaging. 2.5D through-silicon interposer (TSI) is one of the applications of TSV technology, which provides a platform for realizing heterogeneous integration on the TSI interposer. However, TSV manufacturing faces several challenges including high cost. Si-less interconnection technology (SLIT) could overcome such challenges and provide the similar function and benefits as TSI interposer. In SLIT technology, TSVs and silicon substrate are eliminated and the back-end-of-line (BEOL) structures are the same as that in the TSI interposer. Thermo-mechanical reliability is still one important concern under process condition and thermal cycling (TC) test condition for both packaging technologies. In this study, solder joint reliability has been investigated and compared for both packaging technologies through finite element analysis (FEA). Reflow process induced low-k stress and package warpage have also been simulated and compared between packages with TSI and SLIT technologies. The simulation results show that SLIT-based package has comparable micro bump TC reliability as TSI-based package, but SLIT-based package has better C4 joint TC reliability than TSI-based package. SLIT-based package also has lower reflow-induced package warpage and low-k stress than TSI-based package. FEA simulation results verify that SLIT-based packaging is one of promising packaging technologies with good thermo-mechanical performance and cost efficiency. [ABSTRACT FROM AUTHOR]

Highlights: [•] Copper deposition mechanism is stated and mathematical models of the Cu electroplating are established by a series of electrochemical equations. [•] Finite element models (FEM) are built to simulate two different kinds of copper electroplating processes in through-hole via. [•] Experiments show the feasibility of the Cu TSV fabrication under different conditions based on the simulation optimized results. [•] Defect-free Cu TSVs are successfully applied to the Wafer Level Packaging (WLP) Pirani vacuum gauges for the vacuum packaging of MEMS. The devices are proved to be robust and high accuracy. [ABSTRACT FROM AUTHOR]

Abstract: Multi-scale modeling construction and subsequent stress analysis for the mechanical reliability estimation of three-dimensional (3D) integrated circuit (IC) packages is challenging. This paper presents a simulation-based methodology to calculate the equivalent mechanical properties of 3D-ICs through-silicon via (TSV) interposer composed of silicon chip and copper (Cu)-filled metal to resolve this difficulty. The obtained material properties can be utilized in non-concerned regions of analytic structure to reduce modeling complexity significantly and preserve the predicted accuracy in critical locations of 3D-IC packaging simultaneously. The verification of the corresponding analytical solutions ascertains the high reliability of the results predicted by the proposed approach. The results indicate that TSV pitch is a key design factor that dominates the characteristic of a silicon interposer with array-type Cu-filled TSV. The effect resulting from TSV can be ignored as the pitch exceeds 40μm, and pure silicon interposer is assumed to exhibit an isotropic behavior in the related stress assessment using finite element analysis. [Copyright &y& Elsevier]