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Reliability evaluation of integrated circuit (IC) packages to assess drop impact is critical, especially in the case of handheld electronic products. The objective of this study is to experimentally identify the location of damage in solder joints in electronic packaging after a board level reliability (BLR) evaluation. The BLR drop test is a useful way to characterize the drop durability of different soldered assemblies onto a printed circuit board (PCB). It is also of great importance when there is a need to evaluate the solder joint between the chip package and PCB through a daisy-chained structure during the evaluation period. However, there is no detailed information available on a pattern ground with a hatched copper PCB layout for high speed responses that are closely related to actual working conditions. In this paper, a fault location on a daisy-chained structure with a pattern ground is shown through a non-destructive analysis using a time-domain reflectometry (TDR) approach. The results obtained in this project indicate that the TDR approach can be used to detect the location of a crack in the string based on changes in the waveform response. The fault location in critical solder balls as predicted by TDR correlate well with experimental observation by cross-section. [ABSTRACT FROM AUTHOR]

Chip–package interaction (CPI) is becoming a critical issue for the reliability of back-end-of-line (BEOL) during or after package assembly. Complex BEOL layer stacks must have sufficient mechanical strength to survive the thermally induced stresses during processing or working lifetime. Therefore, it is necessary to assess possible failure mechanisms already at early phases of development so that the integrity of the chips can be guaranteed. This paper presents an advanced experimental stability test that combines a BABSI test (Bump Assisted BEOL Stability Indentation test) with in-situ monitoring of the induced stress during this test. A good agreement was found between the applied loads to the BEOL stack, the response of stress sensors below the bump (a Cu pillar) and finite element simulations. [ABSTRACT FROM AUTHOR]

Abstract: Multi-scale modeling construction and subsequent stress analysis for the mechanical reliability estimation of three-dimensional (3D) integrated circuit (IC) packages is challenging. This paper presents a simulation-based methodology to calculate the equivalent mechanical properties of 3D-ICs through-silicon via (TSV) interposer composed of silicon chip and copper (Cu)-filled metal to resolve this difficulty. The obtained material properties can be utilized in non-concerned regions of analytic structure to reduce modeling complexity significantly and preserve the predicted accuracy in critical locations of 3D-IC packaging simultaneously. The verification of the corresponding analytical solutions ascertains the high reliability of the results predicted by the proposed approach. The results indicate that TSV pitch is a key design factor that dominates the characteristic of a silicon interposer with array-type Cu-filled TSV. The effect resulting from TSV can be ignored as the pitch exceeds 40μm, and pure silicon interposer is assumed to exhibit an isotropic behavior in the related stress assessment using finite element analysis. [Copyright &y& Elsevier]