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The Through-Silicon (Si) Via (TSV) is the integration technology for three-dimensional integrated-circuit packaging. The layer-by-layer (LbL) technique has been used to deposit flexible poly(allylamine) hydrochloride (PAH)/polystyrene sulfonate (PSS) multilayers inside scalloped Si trenches of a high aspect ratio, fabricated by the Bosch-etching process. An outstanding control of the thickness and the conformality of the polymer layers, along with a significantly improved planarization, was achieved due to the LbL-technique self-termination effects. In addition, the basic properties of the polymer layers have been characterized: diffusion-barrier properties, adhesion, density, and elastic modulus. The results of this study demonstrate the feasibility of LbL multilayers regarding the TSV liner for the vertical interconnect accesses with a high aspect ratio of highly scalloped surface walls. [ABSTRACT FROM AUTHOR]

Reliability evaluation of integrated circuit (IC) packages to assess drop impact is critical, especially in the case of handheld electronic products. The objective of this study is to experimentally identify the location of damage in solder joints in electronic packaging after a board level reliability (BLR) evaluation. The BLR drop test is a useful way to characterize the drop durability of different soldered assemblies onto a printed circuit board (PCB). It is also of great importance when there is a need to evaluate the solder joint between the chip package and PCB through a daisy-chained structure during the evaluation period. However, there is no detailed information available on a pattern ground with a hatched copper PCB layout for high speed responses that are closely related to actual working conditions. In this paper, a fault location on a daisy-chained structure with a pattern ground is shown through a non-destructive analysis using a time-domain reflectometry (TDR) approach. The results obtained in this project indicate that the TDR approach can be used to detect the location of a crack in the string based on changes in the waveform response. The fault location in critical solder balls as predicted by TDR correlate well with experimental observation by cross-section. [ABSTRACT FROM AUTHOR]

It is challenging to understand and predict interfacial delamination in multi-layered integrated circuit (IC) packaging due to the difficulties in experimentally quantifying the critical fracture energy of interfacial adhesion. This study takes a combined approach based on molecular dynamics (MD) simulation and finite element method (FEM) to characterize the interfacial fracture energy and predict delamination in the Cu/Ti/SiO 2 /Si multilayer systems. MD simulation is first conducted on each interface of the multiple layers at the atomistic level to obtain the material parameters such as the critical interfacial fracture energy that are required for the interfacial cohesive constitutive relation. Then, FEM is used to model and predict the interfacial delamination of the multi-layered system under indentation loading at the macroscale with the cohesive zone being considered around the delamination or crack tips. Finally, the indentation damage test is performed to validate the modeling results. The proposed combined modeling approach will have the potential to provide guidance in design and applications of IC packaging for improved stability and reliability. [ABSTRACT FROM AUTHOR]

Wafer-level characterization of functional prototypes of solid state current sensors is usually the first step in the development stage, therefore a dedicated wafer-level measurement systems are required. Especially for MHz characterization, where electromagnetic interference issues became strongly relevant. Thus, for frequencies above 1 MHz, a sophisticated measurement techniques are needed, because parasitic couplings can significantly affect sensor response and other signal processing stages, causing errors or malfunction of the whole system. We propose technique for high immunity MHz current measurement by solid state sensor in wafer-level configuration. The system is especially well-suited for MHz characterization, where electromagnetic interference issues become highly relevant. We showed that balanced transmission provides possibility to reduce interference in the sensor biasing circuit of about 60 dB compared to single-ended method. The effectiveness of the proposed technique was tested in monitoring MHz current in the external line by single magnetoresistive sensors on wafer level. [ABSTRACT FROM AUTHOR]

Three-dimensional (3D) integration using the through-silicon via (TSV) approach becomes one promising technology in 3D packaging. 2.5D through-silicon interposer (TSI) is one of the applications of TSV technology, which provides a platform for realizing heterogeneous integration on the TSI interposer. However, TSV manufacturing faces several challenges including high cost. Si-less interconnection technology (SLIT) could overcome such challenges and provide the similar function and benefits as TSI interposer. In SLIT technology, TSVs and silicon substrate are eliminated and the back-end-of-line (BEOL) structures are the same as that in the TSI interposer. Thermo-mechanical reliability is still one important concern under process condition and thermal cycling (TC) test condition for both packaging technologies. In this study, solder joint reliability has been investigated and compared for both packaging technologies through finite element analysis (FEA). Reflow process induced low-k stress and package warpage have also been simulated and compared between packages with TSI and SLIT technologies. The simulation results show that SLIT-based package has comparable micro bump TC reliability as TSI-based package, but SLIT-based package has better C4 joint TC reliability than TSI-based package. SLIT-based package also has lower reflow-induced package warpage and low-k stress than TSI-based package. FEA simulation results verify that SLIT-based packaging is one of promising packaging technologies with good thermo-mechanical performance and cost efficiency. [ABSTRACT FROM AUTHOR]

For the objects with repeated motion characteristics such as Integrated Circuit(IC) packaging, Iterative Learning Control (ILC) offers a good scheme for achieving the control of high precise positioning and fast system response. However, in actual production, the performance is significantly deteriorated because of the unavoidable related disturbances when the learning data of a specific position are transferred to other positions, even in the same leading length motion condition. To improve the trajectory tracking performance of the same leading length operations in total workspace, this study proposes an iterative learning controller with wavelet filtering method to eliminate the dependence of iterative learning feed-forward on the special positions of different trajectory conditions. Through the wavelet analysis of the tracking errors with two different starting points, corresponding wavelet coefficients are obtained separately. Then by means of adjusting the wavelet coefficients, the non-consistent disturbance related to positions are removed, thus a universal feed-forward sequence unrelated to the special position is acquired which can be used for trajectory tracking of the same leading length operations in total workspace. Finally, the effectiveness of the proposed method has been demonstrated with the experimental results of a voice coil motor actuating positioning system. [ABSTRACT FROM AUTHOR]

Chip–package interaction (CPI) is becoming a critical issue for the reliability of back-end-of-line (BEOL) during or after package assembly. Complex BEOL layer stacks must have sufficient mechanical strength to survive the thermally induced stresses during processing or working lifetime. Therefore, it is necessary to assess possible failure mechanisms already at early phases of development so that the integrity of the chips can be guaranteed. This paper presents an advanced experimental stability test that combines a BABSI test (Bump Assisted BEOL Stability Indentation test) with in-situ monitoring of the induced stress during this test. A good agreement was found between the applied loads to the BEOL stack, the response of stress sensors below the bump (a Cu pillar) and finite element simulations. [ABSTRACT FROM AUTHOR]

Highlights: [•] Copper deposition mechanism is stated and mathematical models of the Cu electroplating are established by a series of electrochemical equations. [•] Finite element models (FEM) are built to simulate two different kinds of copper electroplating processes in through-hole via. [•] Experiments show the feasibility of the Cu TSV fabrication under different conditions based on the simulation optimized results. [•] Defect-free Cu TSVs are successfully applied to the Wafer Level Packaging (WLP) Pirani vacuum gauges for the vacuum packaging of MEMS. The devices are proved to be robust and high accuracy. [ABSTRACT FROM AUTHOR]

Abstract: Anisotropic microstructure is becoming a critical issue in microbumps used in 3-D integrated circuit packaging. We report here an experimental approach for controlling the microstructure of η-Cu6Sn5 intermetallic compound in microbumps by using 〈111〉 oriented and nanotwinned Cu pads as the under-bump-metallization. By electroplating arrays of large numbers of 〈111〉 oriented and nanotwinned Cu pads and by electroplating the Sn2.3Ag solder on the pads, we form η-Cu6Sn5 in the reflow at 260°C for 1min. The η-Cu6Sn5 showed a highly preferential growth along the 〈0001〉 direction. As reflow time is extended, the preferred texture of η-Cu6Sn5 changed to { }. The results indicate that we can control the uniform microstructure of η-Cu6Sn5 intermetallic by controlling the microstructure of the Cu under-bump-metallization. [Copyright &y& Elsevier]

Abstract: Multi-scale modeling construction and subsequent stress analysis for the mechanical reliability estimation of three-dimensional (3D) integrated circuit (IC) packages is challenging. This paper presents a simulation-based methodology to calculate the equivalent mechanical properties of 3D-ICs through-silicon via (TSV) interposer composed of silicon chip and copper (Cu)-filled metal to resolve this difficulty. The obtained material properties can be utilized in non-concerned regions of analytic structure to reduce modeling complexity significantly and preserve the predicted accuracy in critical locations of 3D-IC packaging simultaneously. The verification of the corresponding analytical solutions ascertains the high reliability of the results predicted by the proposed approach. The results indicate that TSV pitch is a key design factor that dominates the characteristic of a silicon interposer with array-type Cu-filled TSV. The effect resulting from TSV can be ignored as the pitch exceeds 40μm, and pure silicon interposer is assumed to exhibit an isotropic behavior in the related stress assessment using finite element analysis. [Copyright &y& Elsevier]

Abstract: Knowing the Young’s modulus of a plastic molding compound and how it evolves over time and with temperature provides valuable information since it has an important impact on the thermo-mechanical stress that is imposed on a packaged IC. This paper demonstrates the utilization of two techniques that can offer fast, easy and straightforward methods for Young’s modulus extraction of plastic molding compound materials. Both techniques are additionally compared with the nano-indentation (NI) method. Each of these techniques have their advantages and limitations, and therefore, the criterion to select the most appropriate technique for Young’s modulus extraction depends on several parameters like sample preparation time, measurement time and the number of measurements needed to have good statistics. The originality of this study lies in the fact that the evaluation of these methods focuses not only on Young’s modulus extraction from bare molding compound material, but also from molding compounds on packaged IC’s as well. [Copyright &y& Elsevier]

Abstract: Various fine pitch chip-on-film (COF) packages assembled by (1) anisotropic conductive film (ACF), (2) nonconductive film (NCF), and (3) AuSn metallurgical bonding methods using fine pitch flexible printed circuits (FPCs) with two-metal layers were investigated in terms of electrical characteristics, flip chip joint properties, peel adhesion strength, heat dissipation capability, and reliability. Two-metal layer FPCs and display driver IC (DDI) chips with 35μm, 25μm, and 20μm pitch were prepared. All the COF packages using two-metal layer FPCs assembled by three bonding methods showed stable flip chip joint shapes, stable bump contact resistances below 5mΩ, good adhesion strength of more than 600gf/cm, and enhanced heat dissipation capability compared to a conventional COF package using one-metal layer FPCs. A high temperature/humidity test (85°C/85% RH, 1000h) and thermal cycling test (T/C test, −40°C to +125°C, 1000cycles) were conducted to verify the reliability of the various COF packages using two-metal layer FPCs. All the COF packages showed excellent high temperature/humidity and T/C reliability, however, electrically shorted joints were observed during reliability tests only at the ACF joints with 20μm pitch. Therefore, for less than 20μm pitch COF packages, NCF adhesive bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for over 25μm pitch COF applications. Furthermore, we were also able to demonstrate double-side COF using two-metal layer FPCs. [Copyright &y& Elsevier]

Abstract: A cost-effective and simple technique involved in the decapsulation technique of different packages with various epoxy molding compounds (EMCs) attracted a large interest for use in failure analysis of reverse engineering. In this study, we reported that the epoxies molded IC packages with Cu wire bonds were decapsulated using a mixed acid controlled by a jet etcher with minimum degradation of Cu wires and bond interfaces. It was found that the nitric acid to sulfuric acid ratio of 2:1 was the optimum recipe for the preservation of Al pad and Cu wire. We also successfully developed a process both including laser and wet treatments to solve the over-etching and corrosion problems for critical package geometries of ball grid array packages. Additionally, the various physicochemical properties of the wet etching rates for EMCs were also studied using an atomic force micro microscopy, a Kelvin probe force microscopy, and thermo-gravimetrical analyses. [Copyright &y& Elsevier]

Abstract: This paper presents a technological process compatible process compatible with an above integrated circuit (IC) to achieve a millimeter wave antenna structure that is well-suited for wafer level packaging technology. The radiating patch is introduced inside of the air cavity of packaging. This structure consists of two dielectric substrates and benzocyclobutene (BCB) sealing rings at the wafer level. The wafer level packaging that holds the radiating patch is made of Pyrex, a low permittivity substrate. The millimeter-wave antenna using the micromachining technology is excited by a coplanar waveguide fed aperture (CPWFA). This feeding mechanism is designed and realized on GaAs, a high permittivity substrate. The electromagnetic energy of the CPWFA to the radiating patch is made through a coupling slot. The fabricated antenna of 6mm×6mm, including the ground plane, exhibits a 10dB bandwidth of 3GHz from 50.5GHz to 53.5GHz. The design has been driven by the interest of collective encapsulation of MEMS and MMICs devices. [Copyright &y& Elsevier]

Abstract: This research solves a multiresponse simulation problem by using a dual-response system and scatter-search method. The proposed dual-response system constructs a response surface for each response. It then transforms the dual-response problem into a standard non-linear programming formulation. The transformation treats the secondary response as a constraint. In addition, the sample variance from simulation replications is considered simultaneously by adding search area constraints to variance. The proposed scatter-search method uses the scatter-search algorithms as an embedded mechanism in a simulation program to guide the solution-search process. This is an iterative process between the scatter-search algorithms and the simulation program. A practical case study is adopted for empirical illustration. Both the proposed methods are efficient and effective in solving the case-study problem. Finally, the paper discusses the advantages and disadvantages of the proposed methods, and suggests future research opportunities. [Copyright &y& Elsevier]