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In this work, the circuit for unsigned integer restoring division divides each bit in one clock cycle, resulting in total delay cycles equal to the number of bits (n) plus an extra cycle for the final result. Thus, the proposed n-bit division circuit has an access time of (n+1) clock cycles. The hardware cost includes a subtractor and six registers, aligned with a two-phase clocking system. The novelty lies in the shift register, which shifts to the left during the high phase and restores data during the low phase of the clock. Although there are two phases of operations, the subtractor completes a full cycle for computation. As a result, the subtractor's delay time determines the clock period. The control unit is a simple ring shifter triggered at the clock's low phase. The simulation results obtained from synthesized HDL and HSPICE at 90 nm TSMC technology validate the circuit's functionality and characteristic feature of a performance rate of O(n). Using a standard CMOS library component, the 32-bit arithmetic divider requires 33 ns to produce exact Quotient and Remainder values. The circuit operates at a 1 GHz clock cycle and consumes a power of 752 µW. The total number of transistors used in this circuit is 8,860. [ABSTRACT FROM AUTHOR]