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Nowadays, quantum computing plays a significant role in reducing the execution time in complicated computations. There are different reversible algorithms for quantum computation and many quantum circuits theoretically designed until now. These designs are only built from reversible gates because reversibility is a necessary logic in quantum circuits. Additionally, ternary representation can allow designing a circuit with fewer inputs and outputs, leading to a considerable decline in size or number of qutrits. Although other papers in quantum ternary reversible logic are in unbalanced representation, this paper, for the first time, considers balanced ternary advantages to achieve a more efficient design for quantum multipliers as the main component in arithmetic blocks. Six criteria are introduced to show how balanced representation increases the overall performance. In this work, two general balanced ternary adder blocks (full-adder and half-adder) and two balanced ternary partial product generators (BTPPGs) are proposed, and also a 2 × 2 and a 3 × 3 balanced ternary multipliers built from these components. The quantum costs of proposed balanced ternary multipliers enhanced 17% for a 2 × 2 multiplier and 34% for a 3 × 3 multiplier. • radix 3 brings power efficiency, fault tolerance, compactness for quantum computer. • balanced ternary presents more efficient designs for quantum multipliers. • balanced ternary provides better hardware complexity, quantum cost. • balanced ternary offers less garbage output, delay, qutrit number, constant inputs. [ABSTRACT FROM AUTHOR]

This paper discusses heterogeneous Network-on-Chip (NoC) design from a Constraint Programming (CP) perspective and extends the formulation to solving Voltage-Frequency Island (VFI) problem. In general, VFI is a superior design alternative in terms of thermal constraints, power consumption as well as performance considerations. Given a Communication Task Graph (CTG) and subsequent task assignments for cores, cores are allocated to the best possible places on the chip in the first stage to minimize the overall communication cost among cores. We then solve the application scheduling problem to determine the optimum core types from a list of technological alternatives and to minimize the makespan. Moreover, an elegant CP model is proposed to solve VFI problem by mapping and grouping cores at the same time with scheduling the computation tasks as a limited capacity resource allocation model. The paper reports results based on real benchmark datasets from the literature. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a high level power estimation methodology for a Network-on-Chip (NoC) router, that is capable of providing cycle accurate power profile to enable power exploration at system level. Our power macro model is based on the number of flits passing through a router as the unit of abstraction. Experimental results show that our power macro model incurs less than 5% average absolute cycle error compared to gate level analysis. The high level power macro model allows network power to be readily incorporated into simulation infrastructures, providing a fast and cycle accurate power profile, to enable power optimization such as power-aware compiler, core mapping, and scheduling techniques for CMP. As a case study, we demonstrate the use of our model for evaluating the effect of different core mappings using SPLASH-2 benchmark showing the utility of our power macro model. [Copyright &y& Elsevier]

Abstract: There are many design challenges in the hardware-software co-design approach for performance improvement of data-intensive streaming applications with a general-purpose microprocessor and a hardware accelerator. These design challenges are mainly to prevent hardware area fragmentation to increase resource utilization, to reduce hardware reconfiguration cost and to partition and schedule the tasks between the microprocessor and the hardware accelerator efficiently for performance improvement and power savings of the applications. In this paper a modular and block based hardware configuration architecture named memory-aware run-time reconfigurable embedded system (MARTRES) is proposed for efficient resource management and performance improvement of streaming applications. Subsequently we design a task placement algorithm named hierarchical best fit ascending (HBFA) algorithm to prove that MARTRES configuration architecture is very efficient in increased resource utilization and flexible in task mapping and power savings. The time complexity of HBFA algorithm is reduced to O(n) compared to traditional Best Fit (BF) algorithm’s time complexity of O(n 2), when the quality of the placement solution by HBFA is better than that of BF algorithm. Finally we design an efficient task partitioning and scheduling algorithm named balanced partitioned and placement-aware partitioning and scheduling algorithm (BPASA). In BPASA we exploit the temporal parallelism in streaming applications to reduce reconfiguration cost of the hardware, while keeping in mind the required throughput of the output data. We balance the exploitation of spatial parallelism and temporal parallelism in streaming applications by considering the reconfiguration cost vs. the data transfer cost. The scheduler refers to the HBFA placement algorithm to check whether contiguous area on FPGA is available before scheduling the task for HW or for SW. [Copyright &y& Elsevier]

Highlights • BC-NoC is an efficient method to reduce network packet latency. • Proposed RIP BC-NoC partitioning method enhances workload consolidation density. • Task communication minimally uses other application resources. • Application tasks can be mapped close to each other in a straight path. • Increased consolidation density & reduced latency improve performance parameters. Abstract The network on a chip (NoC) is considered as the main shared communication resource to avoid compromise the system performance. A strict isolation strategy is employed in the NoC to avoid performance degradation; however, this strategy is accompanied by a low consolidation density or a complex routing mechanism, which leads to considerable latency and high hardware costs. We propose the row irregular partitioning (RIP) method, which results in a high consolidation density compared to regularity-oriented topology. We additionally propose a congestion awareness (CA) mapping scheme in which mapping is performed based on congestion control on a route in a bypass-channel-based NoC (BC-NoC). Furthermore, mapping methods, such as straight path (SP) and straight path and congestion awareness (SP&CA), are recommended to exploit the communication platform properties of BC-NoC. The experimental results show that the average delay in the SP mapping method is improved compared with SP&CA and CA. [ABSTRACT FROM AUTHOR]

We propose a lightweight scheme where the formation of a data block is changed in such a way that it can tolerate soft errors significantly better than the baseline. The key insight behind our work is that CNN weights are normalized between -1 and 1 after each convolutional layer, and this leaves one bit unused in half-precision floating-point representation. By taking advantage of the unused bit, we create a backup for the most significant bit to protect it against the soft errors. Also, considering the fact that in MLC STT-RAMs the cost of memory operations (read and write), and reliability of a cell are content-dependent (some patterns take larger current and longer time, while they are more susceptible to soft error), we rearrange the data block to minimize the number of costly bit patterns. Combining these two techniques provides the same level of accuracy compared to an error-free baseline while improving the read and write energy by 9% and 6%, respectively. [ABSTRACT FROM AUTHOR]

The balanced ternary representation allows for significant performance improvement for ternary systems. Immaturity of the semiconductor industry in providing an applicable device for ternary infrastructures during the past decades is an enormous obstacle to actualize the ternary circuit realization. Among the promising devices for this purpose, carbon nanotube field effect transistor (CNFET) is qualified with outstanding characteristics which make it suitable for implementing the ternary logic functions. In this paper, for the first time, we present and evaluate the basic ternary arithmetic circuits in balanced representation based on the CNFET technology. Experimental evaluation of reviewed designs in both balanced and unbalanced representation indicates the superiority of the balanced representation in the design of ternary arithmetic blocks. [ABSTRACT FROM AUTHOR]

Recently, Multiple Valued Logic (MVL) has attracted attention, because it reduces the area and complexity of circuits when compared to binary logic. Carbon nanotube field effect transistors (CNFET) are a good candidate for implementing MVL logic circuits, since determining the threshold voltage value of CNFET is easily achievable by changing the diameter of the nanotubes which are placed under the transistor gate. In this paper, quaternary CNFET based 4–2 and 5–2 compressor cells have been proposed. The proposed cell designs were investigated using HSPICE simulator with the standard 32 nm CNFET technology under different operational conditions such as different temperatures, different load capacitances, and different supply voltages. Also the sensitivity to process variations and noise immunity of the proposed designs have been investigated. The proposed quaternary logic designs reduce the delay of the multi operand addition of arithmetic circuits by eliminating the carry propagation overhead. [ABSTRACT FROM AUTHOR]

This paper presents a new ternary operator for cyclic redundancy check in ternary logic with high hardware efficiency. It shows the essential properties of a ternary operator for calculating CRC. Gate-level implementation of CRC-16 is exemplified and comprehensively explained in this paper. Transistor-level realizations of the new and the previous operators are also given in full detail. This paper demonstrates that the employment of the proposed operator reduces hardware components such as the elimination of one entire operator in both transmitter and receiver sides in comparison with ternary SUM . In addition, simulation results by HSPICE and 32 nm CNTFET technology shows about 20.6% energy reduction for one of the implementation methods of the proposed operator with respect to the previously presented one ( CCW CYCLE ). Furthermore, five fewer transistors are needed to design the proposed operator in contrast with both operators SUM and CCW . [ABSTRACT FROM AUTHOR]

In this paper energy-efficient multiple valued logic (MVL) circuits based on carbon nanotube field effect transistor (CNTFET) are proposed. These circuits are designed based on the unique properties of CNTFETs, such as having same mobility for electrons and holes and also capability of adopting desirable threshold voltage by adjusting the CNTs diameters. The proposed designs have high driving capability, larger noise margins and higher robustness as compared to the previous CNTFET-based designs. The proposed quaternary circuits are examined using HSPICE simulator with the standard CNTFET technology. Simulation results demonstrate more energy-efficient and robust operation of the proposed designs, as compared to the other state-of-the-art CNTFET-based MVL circuits, recently presented in the literature. According to the simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45% lower power-delay product (PDP), respectively as compared to their state-of-the-art counterparts. In addition, the proposed QNOT, QNAND and QNOR circuits have the average PDP improvements of 79%, 42% and 61%, respectively, as compared the other recently presented CNTFET-based quaternary designs. [ABSTRACT FROM AUTHOR]

This paper presents a mapping scheme of an optimized octree-based ray tracing algorithm and its implementation on a SIMD reconfigurable architecture, MorphoSys, with appropriate hardware incorporated. A two-level SIMD mapping scheme for ray tracing is chosen to get better trade-off between coherence exploitation efficiency and bandwidth requirements. We apply a SIMD octree traversal algorithm that supports ray traversals of any origins and directions. Moreover, we have applied the bottom-up traversal order for shadow and reflection rays to avoid unnecessary testing. The memory overhead of the parallel execution of ray tracing in SIMD systems is analyzed to direct memory optimization. Pre-fetching is utilized to hide data fetch latency behind the computation. A Spatial Partitioning Tree buffer reduces the latency due to the interleaved accesses to the shared memory. It also dynamically exploits ray coherence to save memory bandwidth. A Pointer Update Unit and a Pointer Buffer are combined to remove the overhead resulted from pointer-calculations and stack pushes during the parallel depth-first-traversal process. The associated hardware cost is less than 2% of the whole system. In order to include diffuse effects into the output, we apply spherical harmonic. Post-synthesis simulation shows that the target chip is estimated to be 33 mm2 and consumes less than 1 W in the worst case. Cycle-accurate simulation demonstrates that interactive ray tracing for medium-sized scenes is achieved on MorphoSys. [Copyright &y& Elsevier]

• A digital fuzzy approach for image edge detection is proposed. • This method employs simple fuzzy rules for digital image edge detection. • Simple logic gates based on carbon nanotube transistor are used for implementation. • Delay and power are significantly reduced while a reasonable accuracy is provided. This study presents a novel digital fuzzy approach for image edge detection based on carbon nanotube field effect transistor (CNTFET). The proposed design employs a simple fuzzy rule for digital image edge detection. To investigate the functionality and performance of the proposed fuzzy approach, our results are compared with the MATLAB edge detection operators such as Sobel, Canny, and Prewitt. Based on the simulation results, we demonstrate that the proposed fuzzy approach can be implemented through nanoscale logic gates and provide a reasonable accuracy. The core element of the proposed fuzzy system, implemented with CNTFETs, occupies 0.22 µm2 layout area and consumes 535 nW power consumption. Our results also emphasize the benefits of the Gate-All-Around (GAA) CNTFETs as a potential candidate for nanoscale digital fuzzy image processing applications. [ABSTRACT FROM AUTHOR]

This paper presents a novel fully programmable membership function generator (MFG) based on carbon nanotube field effect transistors (CNTFETs). The proposed CNTFET-based MFG has full control over the output characteristics such as height, and position independently. The proposed design can produce four different membership functions only by calibrating the external control bias voltages. Moreover, two peripheral transmission gates are utilized to provide controllability over the slope of the generated membership functions in a wide range. The primary advantage of the proposed MFG compared to its counterparts is the ability to control the slope of the resulted membership functions entirely and separately using only two external bias voltages without the need for changing the device physical dimensions. The simulation results demonstrate that the proposed design improves the power, delay, and layout area, on average by, 72%, 55%, and 33% as compared to the previous designs. Furthermore, the proposed MFG shows only 2.13% RMS error, and 5.65% maximum absolute error for the generated Gaussian trapezoidal membership function as compared to the ideal form. Our results certify that the proposed CNTFET-based MFG has the potential to be used as a promising platform for fuzzy inference systems in deep nanoscale technology nodes. [ABSTRACT FROM AUTHOR]