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• We extend, for R and QR data-like MUI and arbitrary propagation channels, the standard two-input SAIC/MAIC WL receivers to data-like MUI with an arbitrary non-zero residual FO, showing that SAIC/MAIC remains possible in this case. • We prove that for a data-like MUI having a non-zero residual frequency offset and spectrally overlapping with the SOI, the extended two-input SAIC/MAIC WL receiver is less efficient for QR signals than for R ones. • We extend, for QR data-like MUI and arbitrary propagation channels, the enhanced three-input SAIC/MAIC WL receiver aleady introduced to data-like MUI with a non-zero residual residual frequency offset, allowing a SAIC/MAIC improvement with respect to the extended two-input SAIC/MAIC WL receivers. • We analyze, both analytically and by simulations, for both R and QR data-like MUI, the impact of the non-zero MUI residual frequency offset on the performance of the proposed extended two and three-input WL FRESH receivers. Widely linear (WL) receivers have been developed in the past for single antenna interference cancellation (SAIC) of one rectilinear (R) or quasi-rectilinear (QR) data-like multi-user interference (MUI) or co-channel interference (CCI) in particular. The SAIC technology has been implemented in global system for mobile communications (GSM) handsets in particular and has been further analyzed for voice services over adaptive multi-user channels on one slot (VAMOS) standard. It remains of great interest for several current and future applications using R or QR signals, such as anti-collisions processing in radio frequency identification (RFID) or in satellite-AIS systems and to densify 5G and Beyond 5G (B5G) networks through one dimensional signaling or over-loaded large MU-MIMO systems. It may be required to cancel the inter-symbol interference (ISI) of control and non-payload communications (CNPC) links of unmanned aerial vehicles (UAV) and the inter-carrier interference (ICI) of filter bank multi-carrier offset quadrature amplitude modulation (FBMC-OQAM), which are now candidate for B5G mobile networks. For these challenging applications, the development of enhanced WL filtering based SAIC or Multiple Antenna Interference Cancellation (MAIC) receivers for R and QR signals may be of great interest. Such a receiver, corresponding to a three-input WL frequency shift (FRESH) receiver, has been introduced recently for QR signals. However this WL receiver is not robust to a data-like MUI having a residual frequency offset (FO), which occurs for most of the previous applications. In this context, the paper first extends, for arbitrary propagation channels, the standards (for R and QR MUI) and the enhanced (for QR MUI) SAIC/MAIC WL receivers to MUI with a non-zero FO. Then, it shows the less efficiency of the two-input WL receiver for QR MUI with a non-zero FO and the performance improvement obtained with the three-input WL receiver. Finally, it analyzes, both analytically and by simulations, for R and QR MUI, the impact of the MUI FO on the performance of the proposed receivers. The results of the paper should allow the development of new powerful WL receivers for UAV CNPC links, anti-collisions AIS systems and for FBMC-OQAM networks in particular. [ABSTRACT FROM AUTHOR]

A new method to induce tensile stress in a PDSOI NMOS device for RF applications is proposed, which is based on relaxing a SiGe layer built underneath silicon. By means of TCAD simulations, we demonstrate that stress transfer from SiGe to Si occurs by means of at least two different mechanisms: SiGe relaxation due to amorphization and the formation of Stacking Faults during recrystallization. By considering both phenomena, a tensile stress of 0.5 GPa can be injected into the silicon channel. Moreover, the impact of annealing steps on the detrimental out-of-SiGe Ge diffusion has been simulated by considering an inter-diffusion model, showing the importance of adapting the PDSOI process flow to account for the presence of the new stressor. [ABSTRACT FROM AUTHOR]

This paper presents a small-signal characterization work on a recently developed 55 nm SiGe BiCMOS technology from STMicroelectronics. The SiGe HBT from a prototype BiCMOS 55 nm process was investigated up to 325 GHz. The full S-parameters from DC to 325 GHz under multiple bias conditions are presented for the first time for a SiGe HBT. A usual and simple approach for the off-wafer calibration associated to an on-wafer de-embedding procedure was used and remained valid up to 325 GHz thanks to a size reduction of the test structures. The extracted 300/325 GHz f T /f MAX couple, reached at 14 mA/μm 2 collector density and 1.2 V collector-emitter voltage, was validated up to 325 GHz. [ABSTRACT FROM AUTHOR]

Optimization of Heterojunction Bipolar Transistors is crucial for improving RF capabilities of modern BiCMOS technologies. Fully-implanted collectors are meant to reduce fabrication complexity and Super Shallow Trench Isolation (SSTI) structures are used to reduce the consequent high base–collector capacitance. Ion implantation can induce lattice defects in silicon and carbon plus phosphorus co-implantation helps reducing them, even if it cannot avoid formation of dislocations generated by bad recrystallization of the implantation-induced amorphous silicon layer. Defects within the device are known to impact functionality and must be avoided. Understanding of the interaction between implantation-induced amorphization and substrate stress due to isolation structures is required for ensuring a reliable integration. Amorphous layer positioning with respect to substrate surface is investigated as the main defect-generation mechanism. Incomplete surface amorphization is shown to induce multiple types of dislocations affecting device functionality. Total surface amorphization ensures almost ideal current characteristics. Silicon clusters appear at high phosphorus/carbon ratios with no impact on functionality. Stress induced by isolation structures is not responsible for dislocations generation but modulates speed of the recrystallization fronts, impacting defects placement. [Display omitted] • Defects can form in substrates doped with amorphizing ion-implantation. • Degree of surface amorphization influences defect formation during Solid Phase Epitaxial Regrowth. • Stress induced by isolation trenches modulates recrystallization speed an therefore defects formation. • Device functionality is impacted by defects within junctions. • Total surface amorphization avoids any recrystallization-induced defect. [ABSTRACT FROM AUTHOR]

Abstract: Vertical and horizontal scaling is aggressively used to increase frequency performances of SiGe Heterojunction Bipolar Transistors. As a result, the evaluation of the extrinsic electrostatic capacitances becomes increasingly important. In this article, we investigate the electrostatic parasitic capacitance in 230–335GHz SiGe transistor technologies. We compare measured electrostatic capacitances with calculations based on a finite elements modelling. We conclude that the influence of the parasitic capacitances only screens the intrinsic performances of the devices by 10–14% but an accurate estimation of theses parasitics must be included in the design of next generation SiGe HBT. [Copyright &y& Elsevier]

The problem of Blind Identification of linear mixtures of independent random processes is known to be related to the diagonalization of some tensors. This problem is posed here in terms of a non-conventional joint approximate diagonalization of several matrices. In fact, a congruent transform is applied to each of these matrices, the left transform being rectangular full rank, and the right one being unitary. The application in antenna signal processing is described, and suboptimal numerical algorithms are proposed. [Copyright &y& Elsevier]

This paper reports an extensive investigation of high frequency figures of merit versus temperature carried out on SiGe:C bipolar transistors with several base doping and activation annealing conditions. The best fT''s are 188 and 278 GHz at 300 and 75 K, respectively. Contributions to total emitter collector delay are discussed and an original method based on collector capacitance measurement is proposed to calculate the collector transit time. [Copyright &y& Elsevier]