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Approximate multipliers play vital role in the error-resilience applications by balancing accuracy and power efficiency. In this article, we improved the accuracy of approximate multipliers using a set of proposed approximate compressors which are able to compress any number of inputs to arbitrary numbers of output bits. To achieve better accuracy, probability of being one in the input bits is used to determine the compression ratio. Also, a novel scheme for allocating approximate and exact compressors in PPM is proposed to decrease column reduction stages. Error metrics namely P E , MED, MRED, and NED are calculated to evaluate accuracy of our approximate compressors. Experimental results show an average of 35% accuracy improvement, in comparison with the previous approximate compressors. We implemented four different multipliers including 8-bit, 12-bit, 16-bit, and 24-bit multipliers to prove goodness of our proposed algorithm. The multipliers are designed by Verilog and synthesized in a 45-nm standard CMOS technology. The experimental results demonstrate major accuracy superiority of our proposed multipliers in comparison with the state of the art approximate multipliers in terms of MED, MRED, and NED. According to the experimental results, the delay is improved 22%, on average, compared with exact multipliers. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a compact, low power 12.5Gb/s backplane receiver in a 90nm CMOS technology. The receiver incorporates an analog equalizer, which is designed using active inductor circuit, and a 1-tap speculative decision-feedback- equalizer (DFE). The proposed active inductor circuit provides wider tuning range and higher inductive impedance with respect to the previous reported topologies, using negative impedance implemented by a cross coupled transistor pair, at the output nodes of active inductor circuit. The DFE is designed in half rate architecture utilizing an improved front end sample and hold to speculate the first feedback tap while consuming low power and imposing small capacitive load on the analog equalizer block. The input capacitance of the DFE block is alleviated more by changing the place of multiplexer in the DFE architecture. Furthermore power consumption reduction in DFE architecture is achieved by using a novel high speed slicer with rail-to-rail swing in the output to avoid implementing latches and MUXs in the next stages in CML topology. The receiver consumes 6.6mW from a 1.2V supply while delivering 12.5Gb/s data over 5″ NELCO 4000-6 channel in the presence of two aggressor far-end-crosstalk (FEXT) signals. [Copyright &y& Elsevier]