Search

Abstract: Achieving high speed and reliability is a key challenge in on-chip bus design. To address the challenge, in this paper we propose a fault model for on-chip communication and further develop a new joint scheme which integrates an equalization technique and special spacing rules for improving the speed and communication reliability for on-chip buses. The proposed equalizer employs a variable threshold inverter whose switching threshold is adjusted as a function of the past output of the buses to achieve high-speed and high-reliability of the buses. Special spacing rules use the sufficient spacing between the adjacent wires to mitigate the crosstalk effect from the adjacent wires. The joint scheme equalization and special spacing rules exploits their respective advantages to further improve the speed and communication reliability of the buses. The simulation results show that the joint scheme equalization and increasing spacing of the uncoded bus can reduce 50% delay and save 42% power only with 52% area overhead compared with the minimum-spaced uncoded bus. The bit error rate of the bus can be improved from 10−5 to 10−24. [Copyright &y& Elsevier]

Abstract: Networks on Chip (NoC) and 3-Dimensional Integrated Circuits (3D IC) have been proposed as the solutions to the ever-growing communication problem in System on Chip (SoC). Most of contemporary 3D architectures are based on Mesh topology, which fails to achieve small latency and power consumption due to its inherent large network diameter. Moreover, the conventional XY routing lacks the ability of fault tolerance. In this paper, we propose a new 3D NoC architecture, which adopts De Bruijn graph as the topology in physical horizontal planes by leveraging its advantage of small latency, simple routing, low power, and great scalability. We employ an enhanced pillar structure for vertical interconnection. We design two shifting based routing algorithms to meet separate performance requirements in latency and computing complexity. Also, we use fault tolerant routing to guarantee reliable data transmission. Our simulation results show that the proposed 3D NoC architecture achieves better network performance and power efficiency than 3D Mesh and XNoTs topologies. [Copyright &y& Elsevier]