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Abstract: Although the incorporation of a SiN capping layer could dramatically enhance device performance, the accompanying hydrogen species contained in the capping layer may aggravate hot-carrier reliability. In order to alleviate this shortcoming, we vary the precursor flow conditions and deposition temperature of SiN film during plasma-enhanced chemical vapor deposition (PECVD) and study their impacts on the device performance and reliability. We found that SiN film with higher nitrogen content depicts larger tensile stress and therefore better mobility. More importantly, the resistance to hot-carrier degradation is also improved by increasing N2 gas flow rate and deposition temperature because of less hydrogen diffusion from the capping layer. [Copyright &y& Elsevier]

Abstract: In this study, the characteristics of DT-pMOSFETs are discussed using the reverse Schottky substrate contacts. With this diode, the DTMOS can be operated at high voltage and temperature. In addition, it exhibited an improved driving current, DIBL, transconductance, and subthreshold slope. The driving current for DTMOS was 20% larger, and was 12mV improved for DIBL under DTMOS operation. Furthermore, the NBTI effects of DTMOS were also reported for the first time. This is because DTMOS could operate just below 0.7V of V G due to the junction turn-on behavior. It is interesting to note that the shift of the ΔV TH of pMOSFETs under NBTI measurement was significantly alleviated in the DT operating mode, about 30mV improved after 10,000s stressing, due to the alleviated electrical field across the gate oxide which was due to the substrate bias and the threshold voltage adjustment under DTMOS operation. [Copyright &y& Elsevier]

Abstract: In this paper, we present a comprehensive study on the effects of layout design and re-crystallization temperature on the material and electrical characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with metal-induced lateral crystallized (MILC) nanowire (NW) channels. It is found that the off-state leakage current shows strong dependence on the arrangement of MILC seeding windows, while the number of smaller solid-phase-crystallized (SPC) grains in the channel is reduced by lowering the re-crystallization temperature, thus improving the on-state behavior. Moreover, owing to the spatial confinement for MILC fronts, small cross-section of the NW channel would result in little lateral crystallization, and thus retarding the enhancement in performance of MILC NW devices. [Copyright &y& Elsevier]

Abstract: We have developed a simple method adopting double-patterning technique to extend the I-line stepper limit for the sub-100nm poly-Si pattern generation in this work. Through in-line and cross-sectional scanned electron microscopic analyses of the generated patterns, we confirmed the feasibility of the double-patterning technique for the fabrication of nano-scale devices. Resolution capability of this technique has been confirmed to be at least 100nm, which is much superior to the resolution limit of conventional I-line lithography. This approach has also been applied for fabricating p-channel metal–oxide-semiconductor field-effect transistors. Excellent device characteristics were verified. [Copyright &y& Elsevier]

Abstract: This study examines the effects of plasma-induced damage (PID) both on advanced SiO2/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal–oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal–oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. [Copyright &y& Elsevier]

Abstract: In this study, the effects of Si3N4 layer capping and TEOS buffer layer inserted prior to the Si3N4 deposition on the NMOS device characteristics as well as correlated hot-electron degradations were investigated. The devices were built on two kinds of the substrates, namely, Cz and hydrogen-annealed (Hi) wafers. More importantly, we found that hydrogen species is the primary culprit for aggravated reliabilities in strained devices. By exerting the accelerated stress test, we could study the hot-electron degradation thoroughly in terms of threshold voltage shift (ΔV TH), transconductance degradation (ΔGm) and so on. The TEOS buffer layer could effectively block the diffusion of hydrogen species from the Si3N4 capping layer into the channel and the Si/SiO2 interface during the Si3N4 deposition as well as subsequent thermal cycles. [Copyright &y& Elsevier]

Abstract: In this paper, we report a conduction-type-tunable carbon nanotube field effect transistor (CNT-FET) with double-gate structure (DG CNT-FET). In this study, a specially designed narrow top-gate is created to modulate the energy band in the middle region of a single CNT. In the proposed DG device structure, the top-gate and bottom-gate biases exhibit independent modulation behaviors. Depending on whether a positive or negative bias is applied to the top-gate, the CNT-FET can be operated in either n- or p-type conduction. Energy band diagram conducive to the physical mechanisms of the proposed DG CNT-FET device structure is proposed. Based on the proposed hypothesis, ambipolar CNT-FETs can indeed be converted to n- or p-type-like behaviors. [Copyright &y& Elsevier]

A novel Schottky barrier silicon-on-insulator metal–oxide–semiconductor field-effect transistor featuring metallic source/drain and an electrical drain junction has been fabricated and characterized. The formation of electrical drain junction, or the field-induced drain (FID), is controlled by a metal field-plate overlying the passivation oxide. Excellent ambipolar operation is demonstrated on the device. Specifically, on/off current ratios up to 108 and 107 are observed for p- and n-channel operations, respectively. Meanwhile, the off-state leakage current shows very weak dependence on the voltage difference between the main-gate and the drain, highlighting the effectiveness of FID. Finally, negative differential conductance effect is observed for n-channel operation, which is identified as due to dynamic hot electron trapping during device characterization. [Copyright &y& Elsevier]

The electrical properties of the metal–ferroelectric–insulator–silicon memories with stacked gate configuration of Pt/SrBi2Ta2O9 (SBT)/Si3N4/p-Si (1 0 0) were investigated. In an attempt to operate at low voltage with sufficient large memory window, various ultra-thin Si3N4 buffer layers in thickness of 3.5, 2, and 0.9 nm were employed. From the results of C–V measurements, the memory window can be as large as 0.8 V at the bias amplitude of 5 V for the sample with 0.9 nm SixNy buffer layer. Well-crystallized perovskite structures have been further confirmed by the spectra of X-ray diffraction measurements. The leakage current, which plays a very important role in the data retention, of Pt/SBT (245 nm)/Si3N4 (0.9 nm)/p-Si (1 0 0) can be as low as 2.5×10−8 A/cm2 at 200 kV/cm. Excellent fatigue-free performance with up to 1010 read/write cycles and good retention time of >2 h have been obtained. Optimization and scaling of SBT thin films are believed to be effective in pursuing extremely low voltage operation, high-density and liable 1T nonvolatile ferroelectric random access memories. [Copyright &y& Elsevier]

A new gate capacitance extraction method from S-parameter measurements is proposed. The distributed nature of MOS transistor and the in-series substrate resistance and in-parallel gate conductance are taken into consideration in the gate capacitance extraction by using high-frequency S-parameter measurements. The error due to dissipation factor can be more effectively reduced by this method, compared to the conventional C–V measurements. Successful extraction of gate capacitance from test transistors with designed test pads has been demonstrated. [Copyright &y& Elsevier]

This paper presents a high performance RF CMOS technology with a complete portfolio of RF and base band components for single-chip systems. Using an optimized 0.13 μm CMOS topology, fT of 86 GHz and fmax of 73 GHz are obtained, in addition to a NFmin of 1.5 dB without ground-shielded signal pad. The high-Q accumulation-mode and diode varactors are optimized to perform a high tuning range of 47% and 25%, respectively. Inductors with a quality factor of 18 at 1.7 nH are obtained using copper interconnect, while capacitors with high unit capacitance and quality factor are fabricated with metal-insulator-metal structures. Finally, a deep n-well isolation is adopted to suppress the interblock coupling noise penetrating through substrate by 40 and 25 dB at 0.1 and 2.4 GHz, respectively. These results clearly demonstrate that CMOS technology can provide a complete solution for single-chip wireless systems. [Copyright &y& Elsevier]