Search

In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to reducing power and energy consumption can show high reliability and have the least error at low voltages. This cell is completely free from the half-select issue, which is one of the important factors in increasing power and decreasing reliability, especially at low voltage levels for SRAM arrays. It is designed without the need of write-bit-line, which according to the proposed techniques reduces the power consumption and significantly improves the write margin, also the lack of this bit-line in the memory array can reduce the total power consumption. The used bit-line only performs for read operation, therefore it has least activity. Also, an 8 Kb memory array is proposed to be able to perform various operations with less complexity, simpler logic and lower power consumption by proposing several techniques on peripheral circuits. All obtained noise margins according to proposed techniques have the highest values among the compared cells. The average power and PDP of the cell are less than all the compared designs, so that the average power and presented FoM has been improved by 6.83% and 18.46% respectively as compared to the best value of other designs. [ABSTRACT FROM AUTHOR]

In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to reducing power and energy consumption can show high reliability and have the least error at low voltages. This cell is completely free from the half-select issue, which is one of the important factors in increasing power and decreasing reliability, especially at low voltage levels for SRAM arrays. It is designed without the need of write-bit-line, which according to the proposed techniques reduces the power consumption and significantly improves the write margin, also the lack of this bit-line in the memory array can reduce the total power consumption. The used bit-line only performs for read operation, therefore it has least activity. Also, an 8 Kb memory array is proposed to be able to perform various operations with less complexity, simpler logic and lower power consumption by proposing several techniques on peripheral circuits. All obtained noise margins according to proposed techniques have the highest values among the compared cells. The average power and PDP of the cell are less than all the compared designs, so that the average power and presented FoM has been improved by 6.83% and 18.46% respectively as compared to the best value of other designs. [ABSTRACT FROM AUTHOR]

In this paper, a robust 12T-SRAM memory cell at sub-threshold voltage is designed to reduce power consumption for low power applications, that in addition to reducing power consumption can perform well at high frequencies and remain stable. For the write operation, a new method has been used that removes the write bit line and uses the supply voltage in each cell for this operation and only by applying control signals. Also, the embedded bit line is used only for read operations and reduces the activity of the bit line, and due to being floating and the way of writing, eliminates the Precharge and Write Driver circuits, so, part of the power and area consumption has been reduced. According to the techniques used, the write and read noise margin is significantly improved and the write operation become easier to perform. Also due to the existence of a separate path for the read operation, RSNM is equaled to the HSNM. The average cell power at the frequency of 100 MHz for low power applications and 0.2V supply voltage, as compared to the best previous designs, has been improved by 34.9% and the leakage power of the hold state has been reduced by 27.6% and PDP has been improved by more than 35.2%, further, the maximum operating frequency of the cell has been increased by 39.1%, while it operates with the sub-threshold voltage of 0.2V to the frequency of 2.173 GHz. [ABSTRACT FROM AUTHOR]

Multipliers are one of the most commonly used parts in a system, responsible for performing computations, while significantly contributing to power consumption. In this article, by removing the least significant bits, a new architecture is presented to implement 3 multipliers (Mul-1, Mul-2 and Mul-3), in order to reduce complexity and power consumption. Compared to the previous works, Mul-1 has the most accuracy in addition to its low energy consumption, therefore, it has been able to deliver a good trade-off between accuracy and energy consumption. All proposed designs and existing multipliers have been simulated and compared in 7 nm FinFET technology using Hspice tool. Moreover, the accuracy and quality of the proposed approximate multipliers are also evaluated using MATLAB. The results show that Mul-1 and Mul-3 are very efficient in image processing applications. According to the results, Mul-1 outperforms its counterpart by 10%, 50% and 50% in PDP, NMED and MRED, respectively. Furthermore, Mul-3 has satisfactory MSSIM in DSP applications and is better than its counterpart by 23% and 16% in PDP and MRED. Meanwhile, Mul-2 improves PDP by nearly 53% compared to Mul-1 and has the lowest power consumption. [Display omitted] • To reduce power consumption, some least significant bits are set to zero. • To ensure accuracy in multipliers, compressors have been employed as exact. • The error compensation circuit is presented to enhance precision in the second stage. • The use of multipliers in real applications that have high computational volume. [ABSTRACT FROM AUTHOR]