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This paper investigated DRAM DIMM errors using field records in replacement network servers. Large DRAM samples of about 40 K were collected over a 2.5 years period from 23 different server types, included various DIMMs from three different DRAM manufacturers with densities between 4 and 128 GB, and speeds between 1066 and 2400 Mbps. Errors that occurred during system operation were classified as either correctable (CE) or uncorrectable (UE) errors based on error correction code (ECC) schemes built into the servers. Of the collected DIMMS, 24% had recorded errors, where CE-only, UE-only, and UE and CE together comprised 28%, 43%, and 29% of recorded errors, respectively. Since UEs can cause large-scale failures, systems are replaced upon any UE occurrence. Approximately half UE-only DIMMs had 1 UE error. In contrast, many DIMMs had billions of CE errors, where a faulty location may be repetitively accessed. Such drastic differences in UE and CE counts help explain the importance of ECC and error mitigation schemes. Comparative analyses of errors were made over the manufacturers and operating speeds. After reasonable adjustments for repetitive counts of errors, failure in time (FIT) differences were up to 38% over manufacturers. Higher speed DIMMs generally had higher FIT with 2400 Mbps DIMMs exhibiting 6.7 times FIT of 1066 Mbps DIMMs. [ABSTRACT FROM AUTHOR]

This paper proposes a new method of investigating the effect of void or fracture in FBGA solder ball on the DDR4 data signal rise time and inter-symbol interference (ISI), by loading the data line with a capacitor. A void or fracture in solder ball increases its capacitance which effects the data signal rise time and increases ISI. For measuring ISI large consecutive patterns of 1's or 0's followed by a changing bit are used. However in in-field systems it is not possible to run large patterns of 1's or 0's. So the data line is loaded with a 0.2 pF capacitive load on a UDIMM test card to mimic the increased capacitance due to FBGA solder ball void defect of height 0.2 mm and cross sectional area of 0.0045 mm2. The loaded line shows increase in rise time of 16 ps. For loaded line the data eye opening is 0.077 UI lesser. This decrease in data eye means more ISI and will cause increase in intermittent errors. • Proposes a new method of investigating the effect of void or fracture in FBGA solder ball • A capacitor is loaded on the DDR4 data line to mimic the effect of FBGA fault • Rise time of the data signal with capacitive load shows increase • Channel loss of the data line with capacitive load shows increase hence more intermittent errors [ABSTRACT FROM AUTHOR]