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It is well-established that oxide defects adversely affect functionality and reliability of a wide range of microelectronic devices. In semiconductor-insulator systems, insulator defects can capture or emit charge carriers from/to the semiconductor. These defects feature several stable configurations, which may have profound implications for the rates of the charge capture and emission processes. Recently, these complex capture/emission events have been investigated experimentally in considerable detail in Si/SiO 2 devices, but their theoretical understanding still remains vague. In this paper we discuss in detail how the capture/emission processes can be simulated using the theoretical methods developed for calculating rates of charge transfer reactions between molecules and in electro-chemistry. By employing this theoretical framework we link the atomistic defect configurations to known trapping model parameters (e.g. trap levels) as well as measured capture/emission times in Si/SiO 2 devices. Using density functional theory (DFT) calculations, we investigate possible atomistic configurations for various defects in amorphous ( a )-SiO 2 implicated in being involved in the degradation of microelectronic devices. These include the oxygen vacancy and hydrogen bridge as well as the recently proposed hydroxyl E ′ center. In order to capture the effects of statistical defect-to-defect variations that are inevitably present in amorphous insulators, we analyze a large ensemble of defects both experimentally and theoretically. This large-scale investigation allows us to prioritize the candidates from our defect list based on their trap parameter distributions. For example, we can rule out the E ′ center as a possible candidate. In addition, we establish realistic ranges for the trap parameters, which are useful for model calibration and increase the credibility of simulation results by avoiding artificial solutions. Furthermore, we address the effect of nuclear tunneling, which is involved according to the theory of charge transfer reactions. Based on our DFT results, we demonstrate the impact of nuclear tunneling on the capture/emission process, including their temperature and field dependence, and also give estimates for this effect in Si/SiO 2 devices. [ABSTRACT FROM AUTHOR]

Metal-oxide-semiconductor (MOS) devices are affected by generation, transformation, and charging of oxide and interface defects. Despite 50 years of research, the defect structures and the generation mechanisms are not fully understood. Most light has been shed onto the charging mechanisms of pre-existing oxide defects by using the non-radiative multi-phonon theory. In this work we present how the gist of physical models for pre-existing oxide defects can be efficiently abstracted at a minimal loss of physical foundation and accuracy. Together with a semi-empirical model for the generation and transformation of defects we establish a reaction-limited framework for unified simulation of bias temperature instabilities (BTI). The applications of the framework we present here cover simulation of BTI for negative (NBTI) and positive (PBTI) gate voltages, life time extrapolation, AC stress with arbitrary signals and duty cycles, and gate stack engineering. [ABSTRACT FROM AUTHOR]

A paradigm for MOSFET instabilities is outlined based on gate oxide traps and the detailed understanding of their properties. A model with trap energy levels in the gate dielectric and their misalignment with the channel Fermi level is described, offering the most successful strategy to reduce both Positive and Negative Bias Temperature Instability (PBTI and NBTI) in a range of gate stacks. Trap temporal properties are determined by tunneling between the carrier reservoir and the trap itself, as well as thermal barriers related to atomic reconfiguration. Trap electrostatic impact depends on the gate voltage and its spatial position, randomized by variations in the channel potential. All internal properties of traps are distributed, resulting in distributions of the externally observable trap parameters, and in turn in time-dependent variability in devices and circuits. [ABSTRACT FROM AUTHOR]

As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability-related variability) is an emerging concern that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-called defect-centric picture in terms of an ensemble of individual defects. The properties of gate oxide defects are discussed. It is further shown how in particular the electrical properties can be used to construct time-dependent variability distributions and can be propagated up to transistor-level circuits. [ABSTRACT FROM AUTHOR]