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Abstract: A Lead Zirconate-Titanate (PZT)/poly-dimethylsiloxane (PDMS) based flexible composite is synthesized and investigated for its potential in significantly enhancing the vibration damping capability along with its tunable properties. Rheologically and functionally different PZT/PDMS composites are prepared by dispersing different volume fractions of piezoelectric soft/hard PZT and Fe particles in a cross-linked PDMS matrix. It is observed that passive damping increases with increase in the soft PZT volume fraction from 0 to 0.32. This effect becomes more prominent after poling the composite at optimum conditions. The loss factor depends on the viscoelastic properties of the PDMS, homo and hetero-particle connectivity in the composite, and polarization and localization of the PZT particles in composite. Rheological analysis of the composite shows that the material loss factor (tan δ) increases linearly from ∼0.3 to 0.75 along with a broadening of the peak when the PZT volume fraction is increased from 0 to 0.32. Maximum structural damping (η) is obtained at 0.32 (V/V) of the soft-PZT as measured by the Oberst beam technique. This effect becomes more pronounced after a poling treatment. The X-ray diffraction results indicate that the dispersed PZT particles in PDMS matrix have the lattice parameters of a =5.84Å, c =14.41Å and (001) orientation. Further, after poling treatment, the dielectric constant and the piezoelectric coefficient (d 33) for soft (submicron) PZT filler particles in PDMS matrix tend to be higher than those for hard PZT. The soft PZT/PDMS composite shows better performance as a damper than the hard, PZT composite. [Copyright &y& Elsevier]

Abstract: Thin silicon oxynitride (SiO x N y ) films were deposited by low temperature (∼300°C) plasma enhanced chemical vapour deposition (PECVD), using SiH4, N2O, NH3 precursor of the flow rate 25, 100, 30sccm and subjected to the post deposition annealing (PDA) treatment at 400°C and 600°C for nano optical/photonics on chip interconnects applications. AFM result reveals the variation of roughness from 60.9Å to 23.4Å after PDA treatment with respect to the as-deposited films, favourable surface topography for integrated waveguide applications. A model of decrease in island height with the effect of PDA treatment is proposed in support of AFM results. Raman spectroscopy and FTIR measurements are performed in order to define the change in crystallite and chemical bonding of as-deposited as well as PDA treated samples. These outcomes endorsed to the densification of SiO x N y thin films, due to decrease in Sice:glyph name="sbnd" />O bonds strain, as well the Olyph name="sbnd" />H bonds with in oxynitride network. The increase in refractive index and PL intensity of as deposited SiO x N y thin films to the PDA treated films at 400°C and 600°C are observed. The significant shift of PL spectra peak positions indicate the change in cluster size as the result of PDA treatment, which influence the optical properties of thin films. It might be due to out diffusion of hydrogen containing species from silicon oxynitride films after PDA treatment. In this way, the structural and optical, feasibility of SiO x N y films are demonstrated in order to obtain high quality thin films for nano optical/photonics on chip interconnects applications. [Copyright &y& Elsevier]

Abstract: The effect of rapid thermal annealing on structural and electrical properties of high-k HfO2 ultra thin films deposited by rf-sputtering system is investigated. The films properties were investigated for optimum rapid thermal annealing temperature in oxygen and nitrogen ambient, respectively to get the best electrical results as a MOS device structure. Detailed studies of temperature induced annealing effects on the HfO2/Si interface are done using Fourier Transform Infrared Spectroscopy (FT-IR). The film thickness, composition and microstructure is studied by Ellipsometry, XRD and AFM, respectively, and the effect of annealing on these parameters is shown. The I–V and C–V characteristics of the annealed dielectric film were investigated employing Si/HfO2/Si MOS capacitor structure. The results showed that the HfO2/Si stack with rapid thermal annealing (RTA) in nitrogen ambient showed improved physical and electrical performance than with in oxygen. It is shown that RTA improves the interface properties of HfO2/Si and the densification of HfO2 ultra thin films. The as deposited films were amorphous and orthorhombic after annealed at 700°C in nitrogen and oxygen, respectively. We found that the nitrogen annealed samples exhibit a reduced equivalent oxide thickness, interfacial density of states, capacitance–voltage hysteresis and leakage current; additionally it also showed negligible charge trapping under positive voltage bias and temperature stress. The results are presented and discussed. [Copyright &y& Elsevier]

Abstract: The effect of constant negative voltage stress on charge trapping and interface states of Al/HfO2/SiO x N y /Si structures are investigated. The reduction in the capacitance of C–t characteristics and a significant shift in C–V curves towards negative voltage axis reveal that the charge trapping/detrapping occurs at the Si/SiO x N y /HfO2 interface and HfO2 bulk. However, there is a relative increase in gate leakage current as a function of the voltage stress and time, owing to the trap-assisted tunnelling. It is suggested that these traps are probably Hf–OH neutral centers, originating from the breaking of bridging Si–OH and Si–NH bonds by mobile H+ protons. This has potential application in non-volatile CMOS memory devices. [Copyright &y& Elsevier]

Abstract: Integrating digital, analog, I/O and memories onto a single chip is a great challenge to the design and process engineers. From the process engineers'' point of view, integrating these modules with conflicting requirements needs a lot of innovation in the process technology. One such requirement is the need of having multiple gate oxide thickness on the same chip. Fluorine implantation of variable doses is explored to achieve this goal. It has been found that by varying the implanted dose of the fluorine in silicon, the oxidation rate and thereby the oxide thickness can be varied. The electrical characterization of the fluorine-implanted silicon based MOS structures using C–V and J–E measurements is reported here. It has been found that one can control the oxide thickness, interface properties and threshold voltage that could be vital in the SOC level integration. [Copyright &y& Elsevier]

Abstract: The integration of entire system on a chip (SOC) is the major challenge for the semiconductor industries. The successful implementation of SOC will require innovation in both circuit design and fabrication technology. However, from a process technology point of view, it can be seen that in order to provide design flexibility each of the sub-system may require different gate oxide thicknesses. In this work, 19F+ implantation of variable doses on silicon is explored to achieve this goal. It has been observed that the differential oxide thickness can be achieved by varying the implanted dose of the fluorine on silicon, due to alteration in the oxidation rate. C–V and J–E characteristics are used to demonstrate the electrical behavior of fluorine implantation-based MOS devices. The stoichiometric composition analysis of dielectric materials is reported by FTIR measurements. The control over the oxide thickness, interface states, threshold voltage and stoichiometric composition of dielectric materials could play a vital role in the SOC level integration. [Copyright &y& Elsevier]

Metal–Ferroelectric–Insulator–Semiconductor (MFIS) thin film capacitors with lead zirconate titanate (Pb(Zr 0.52 Ti 0.48 )O 3 ) as ferroelectric layer and ultrathin high-κ titanium oxynitride (TiO x N y ) as insulating buffer layer on p-Si are fabricated by RF magnetron sputtering for non-volatile multilevel ferroelectric random access memory (FeRAM). Micro Raman analysis of the proposed systems confirmed the existence of most stable tetragonal rutile phase in ultrathin TiO x N y and perovskite phase of PZT thin films. AFM analysis showed that surface roughness of ultrathin TiO x N y and thin PZT films are ∼2.54 nm and ∼1.85 nm, respectively and result the uniform interface between substrate and metal. The maximum C – V memory window of ∼1.25 V was obtained at cyclic sweep voltage of ±6 V and starts to decrease when the sweep voltage exceeds 6 V due to charge injection. The fabricated structure possesses good data retention measured till 1.5 h and high, low capacitance states remain distinguishable even if extrapolated to 15 years. The proposed system exhibited excellent TiO x N y –Si interface, incomparable high breakdown field strength ∼11.15 MV/cm and low leakage current density ( J ) ∼5 μA/cm 2 at +4 V. Thus, Au/PZT/TiO x N y /Si MFIS based FeRAM devices with multilevel operation, high breakdown field and excellent retention are prospective contender for next generation multilevel FeRAM technology node. [ABSTRACT FROM AUTHOR]

An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity is imposed on capacitive DAC; replacing capacitor bank with only a one switch-capacitor circuit. The regulated dynamic current mirror (RDCM) design is introduced to provide stabilized current. This invariable current from RDCM, charging or discharging the only capacitor in circuit is controlled by pulse width modulated signal to realize switch capacitor DAC. The switch control scheme is built using basic AND gates to generate the control signals for RDCM. Only one capacitor and reduced transistor count in digital part reduces the silicon area occupied by the ADC to only 0.0098 mm 2 . The converter, designed in GPDK 90 nm CMOS, exhibits maximum sampling frequency of 100 kHz & consumes 6.75 µW at 1 V supply. Calculated signal to noise and distortion ratio (SNDR) at 1 V supply and 100 kS/s is 48.68 dB which relates to ENOB of 7.79 bits. The peak values of differential and integral nonlinearity are found to be +0.70/−0.89 LSB and +1.40/−0.10 LSB respectively. Evaluated figure of merit (FOM) is 3.87×10 20 , which show that the proposed ADC acquires minimal silicon area and has sufficiently low power consumption compared to its counterparts in RFID applications. [ABSTRACT FROM AUTHOR]

Abstract: We report the first investigation of the frequency dependent effect of 50MeV Li3+ ion irradiation on the series resistance and interface state density determined from capacitance–voltage (C–V) and conductance–voltage (G–V) characteristics in HfO2 based MOS capacitors prepared by rf-sputtering. The samples were irradiated by 50MeV Li3+ ions at room temperature. The measured capacitance and conductance were corrected for series resistance. The series resistance was estimated at various frequencies from 1KHz to 1MHz before and after irradiation. It was observed that the series resistance decreases from 6344.5 to 322Ω as a function of frequency before irradiation and 8954–134Ω after irradiation. The interface state density D it decreases from 1.12×1012 eV−1 cm−2 before irradiation to 3.67×1011 eV−1 cm−2 after ion irradiation and further decreases with increasing frequency. [Copyright &y& Elsevier]

[Display omitted] • A i-BPPV has been fabricated by incorporating perovskite material between the transparent bottom electrode (ITO) and top electrode (Au/ITO). • The champion i-BPPVs exhibited an efficiency of 30.3% and 22.1% for top- and bottom-side, respectively, when LED artificial light source of 1000 lx. • The bifacial i-BPPVs display an excellent bifaciality factor (Φ) of 0.73. • Hysteresis loss decreased as bifacial devices were exposed from both-sides (top- and bottom-sides) under indoor light source. Emerging bifacial photovoltaics (BPVs) have received tremendous attention due to their high efficacy and economical cost by harvesting more light energy in outdoor conditions. Although, the performance of BPVs in outdoor conditions is severely limited by the albedo light (light reflected from the surface, soil, clouds, etc.). Conversely, BPVs could also be utilize to efficiently harvest energy from indoor environments such as offices, homes, large gathering halls, stations, and more, where multiple artificial lighting sources are employed. In this work, we have designed an efficient indoor bifacial perovskite photovoltaics (i-BPPVs) with the capability of harvesting maximum light from both top and bottom sides. The i-BPPVs were designed and fabricated in a stack of organic–inorganic hybrid perovskite material amid a transparent bottom electrode (ITO), and top (Au/ITO) electrode. The fabricated i-BPPVs exhibited an efficiency of 30.3%, short circuit current density (J SC) of 148.3 µA cm−2, open circuit voltage (V OC) of 0.93 V, and fill factor (FF) of 71.7% when artificial LED light source of 1000 lx is exposed from the top side, whereas an efficiency of 22.1%, J SC of 116.2 µA cm−2, V OC of 0.89 V, and FF of 69.4% have been obtained from the bottom side. The champion bifacial i-BPPVs display an excellent bifaciality factor (Φ) of 0.73 and demonstrated superior operational stability when subjected to continuous illumination. Moreover, this work of designing i-BPPVs will be a pivotal step towards advancing cost-effective and efficient technology for harvesting more energy from artificial indoor light sources. [ABSTRACT FROM AUTHOR]