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Abstract: We examined temperature dependence of the I c R n (I c being the critical current and R n being the normal-state resistance) product for interface-engineered YBa2Cu3O7−x ramp-edge junctions formed on a groundplane. There were two types for the temperature dependence of the I c R n product. One was the linear temperature dependence, and the other was a dependence that shows the steeper drop with temperature. There were two factors that were responsible for the temperature dependence of the I c R n value. These were critical temperature T c of the junctions and temperature dependence of the R n value. The I c R n value more than 1mV at 40K was obtained for the junction that had the T c of 84K and the positive coefficient of R n value on temperature. [Copyright &y& Elsevier]

We have investigated the flux state in high-Tc circuits based on multilayer structures including La-doped YBCO (La-YBCO) ground plane by a scanning SQUID microscope (SSM) system. The circuits contained via holes in the insulating layer and the ground plane. They were post-annealed in flowing oxygen under various conditions such as the annealing temperature and the annealing time. It was found that the flux state depends on the post-annealing temperature strongly, and in the case of annealing at temperatures lower than 500 °C, oxygen is not provided into the ground plane sufficiently. Moreover, we found that oxygen via holes are necessary to provide oxygen sufficiently into the ground plane, and an appropriate via hole configuration is needed for homogeneous oxidation. [Copyright &y& Elsevier]

Abstract: We proposed a novel multilayer structure having a new combination of oxides for integrated high-T c SQUID with ramp-edge Josephson junctions. La0.1Er0.95Ba1.95Cu3O y (L1ErBCO) and SmBa2Cu3O y (SmBCO) were used as counter- and base-electrodes, respectively. An SrSnO3 (SSO) layer was deposited as an insulating layer. Prior to deposition of SmBCO, Pr1.4Ba1.6Cu2.6Ga0.4O y (P4G4) and SSO were deposited on MgO (100) substrate in order to improve film quality of L1ErBCO/SSO/SmBCO layers. The black-colored P4G4 layer was expected to work as a temperature homogenizer over a whole substrate area during deposition of the upper layers. All the layers except L1ErBCO were deposited by an off-axis magnetron sputtering. An L1ErBCO layer was deposited by a pulsed laser deposition method. A thin Cu-poor L1ErBCO layer was initially deposited to form an adequate barrier on the ramp-edge of SmBCO. Gradiometer arrays having multilayered feedback coils and pickup loops were made in a chip and their proper operation at 77K was confirmed. The present multilayer structure is promising for application to SQUIDs with more complicated designs. [Copyright &y& Elsevier]

Abstract: We have investigated the flux state in YBa2Cu3O y (YBCO) sampler circuits having superconducting ground planes with 5 or 7-μm-wide moats by a scanning SQUID microscope (SSM) system. It was found that magnetic flux was trapped into continuous moats with the length larger than 20μm, and magnetic flux was excluded from the moat-surrounded area which includes ramp-edge Josephson junctions and ground plane contacts. We ensured that flux trapping into ground plane contacts is suppressed by reducing its size to typically 5×5μm2. The threshold value for complete flux exclusion is about 0.8μT slightly depending on chips, which can be readily achieved with dual μ-metal magnetic shielding. In addition, we have observed the magnetic flux due to electric noise which comes from outside the SSM chamber. [Copyright &y& Elsevier]

Abstract: We examined the deposition conditions for SrSnO3 films with a smooth surface and good crystallinity on both ground plane (GP) and MgO substrate, and successfully found the optimum conditions. SrSnO3 insulating layers were prepared by an rf magnetron sputtering method. SrSnO3 films deposited at gas pressure of 80mTorr (Ar+50% O2) and rf power of 50W with optimized target-substrate configuration had a smooth surface with the average roughness R a less than 1nm. The measured X-ray rocking curve for the (200) reflection peak showed a small FWHM value of 0.3°. X-ray fluorescence analysis (XRF) and inductively coupled plasma analysis (ICP) revealed that the Sn/Sr cationic ratio for the films were close to unity. Employing the optimized SrSnO3 films, we fabricated interface-engineered ramp-edge junctions on a patterned GP. The fabricated junctions exhibited RSJ-type I–V characteristics with I c R n products of about 2.1mV at 4.2K. [Copyright &y& Elsevier]

We have tried to improve the ramp-surface morphology by modifying the film surface morphology (base-YBCO electrode and LSAT isolation layer) and the ion etching conditions. The relationships between the ramp-surface morphology and the Ic-spreads for interface-engineered junctions are investigated. By applying a mechanical polishing technology to YBCO and LSAT films prepared by PLD, the average roughness is substantially decreased. The junctions with a smooth ramp-surface fabricated by employing the polishing technique or sputtered bilayer films exhibited an Ic-spread of 14.5% for a 120JJ-array with an average Ic of approximately 1 mA. It is found that the roughness of ramp-surface is further decreased with decreasing the acceleration voltage during etching with a large-diameter ion gun. The Ic-spread of the JJ-array is decreased to 11% for a similar average Ic. By employing etching at a lower acceleration voltage for a longer time, a good Ic-spread of 17% for 1000JJs is obtained in spite of a much smaller average Ic of 0.1 mA. These results indicate that use of sputtered YBCO films or polished PLD films, and uniform-beam etching at a lower acceleration voltage for a longer time are advantageous to improvement of junction uniformity. [Copyright &y& Elsevier]

We have fabricated interface-modified ramp-edge junctions with sputtered La-doped YBa2Cu3Oy (La-YBCO) and La-doped YbBa2Cu3Oy (La-YbBCO) by pulsed laser deposition as base and counter-layers, respectively. The influences of deposition parameters for the La-YbBCO counter-layers on the electrical properties and Ic spread of the junctions are investigated. Junctions with resistively and capacitively shunted junction-like I–V characteristics and a typical IcRn of 2–3 mV at 4.2 K can be fabricated in the substrate temperature range of 640–700 °C. By optimizing the deposition parameters including the target–substrate distance, a 1σ spread in Ic as small as 8.7% is obtained for 25-junction series array. [Copyright &y& Elsevier]