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The effect of pre–metal deposition cleaning on 4H-SiC Schottky barrier diodes (SBDs) by using Ar ion bombardment in an inductively coupled plasma (ICP) chamber was investigated. The ICP treatment produced a thin and Si-depleted amorphous layer on the SiC surface. Partial graphitization was observed in the amorphous layer after post-metal deposition (PMD) annealing. This interfacial layer strongly pinned the Schottky barrier height (SBH). PMD annealing at 500 °C resulted in a constant SBH (approximately 1.1 eV) and narrow SBH distribution (standard deviation < 3 meV). However, the amorphous layer was consumed after 600 °C PMD annealing due to interfacial reactions. These results suggest that the Ar ion bombardment technique with a suitable thermal budget can be used to form relatively uniform SBDs. [ABSTRACT FROM AUTHOR]

In this work, the effect of dopant segregation on the NiGe/n-Ge contact is studied by experiments and first-principles calculations. Both Al-contacted and NiGe-contacted n + /p junctions were fabricated. Phosphorus and arsenic ions were Implanted Before Germanide (IBG) formation or Implanted After Germanide (IAG) formation. The NiGe-contacted junction always exhibit higher forward current than the Al-contacted junction due to dopant segregation. First principles calculations predict that phosphorus atoms tend to segregate on both NiGe side and Ge side while arsenic atoms tend to segregate at Ge side. Since phosphorus has higher activation level and lower diffusion coefficient than arsenic, we propose a phosphorus IBG + arsenic IAG process. Shallow n + /p junction with junction depth 90 nm below the NiGe/Ge interface is achieved. The lowest and average contact resistivity is 2 × 10 −6 Ω cm 2 and 6.7 × 10 −6 Ω cm 2 , respectively. Methods which can further reduce the junction depth and contact resistivity are suggested. [ABSTRACT FROM AUTHOR]

Highlights: [•] Comparing the performance of CNT-interconnects with four combinations. [•] Improving the electrical properties and reliabilities by double layer structures. [•] Demonstrating the size and structure percolative conductance of CNT-interconnects. [•] Proposing further work for the CNT-interconnect optimization. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, a simple and low temperature fabrication process, slow spin rate coating and dry etching, is proposed to construct the CNT-interconnects for future VLSI interconnect applications. Two sets of CNT-interconnects named width and length varying interconnects were fabricated to investigate the characterization of size dependent conductivity of CNT-interconnects. Not only the amount of the CNT solution spin-coated for forming the CNT networks but also the area of CNT-interconnect regime would affect the conductance, variation, and conductive probability of CNT-interconnects. The yield of working CNT-interconnects does not show direct relation with the conductive probability or the amount of the CNT solution for CNT network formation. Based on the percolation theory, we characterize the average conductance of size-varying CNT-interconnects by three regions: percolation region, power region and linear region. In addition, as the density within a specified CNT-interconnect regime accumulates, the conductive behavior would be eventually characterized as a conventional resistor. [Copyright &y& Elsevier]

Abstract: Effect of surface preparation on the radiation hardness of MOS devices with high dielectric constant gate dielectric of HfO2 and metal gate of TiN is studied using extreme ultra-violet (EUV) light as the radiation source. Three kinds of surface treatment including HF-last, chemical-oxidation, and rapid-thermal-oxidation were evaluated. Among them, chemical-oxidation exhibits the best radiation hardiness in terms of interface traps and border traps. The state-of-the-art MOSFET with a thin high-k dielectric and a high quality chemical oxide interfacial layer shows that the degradation of subthreshold swing is more severe than degradation of threshold voltage. However, the overall degradation is less than 6% even after EUV irradiation to a total dose of 580mJ/cm2. Off-state current degradation is observed due to the generation of oxide traps and interface traps at the isolation region. This phenomenon does not occur in the conventional optical lithography process but should be considered if EUV lithography is used. [Copyright &y& Elsevier]

Abstract: Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139mV/dec, high transconductance of 1.27μS, and high I on/I off ratio of 106 can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future. [Copyright &y& Elsevier]

Abstract: Multi-gate non-volatile memory (NVM) cell is a promising approach in the next generation. In this work, the performance of NVMs using nanocrystals (NCs) and nanowires (NWs) as charge trapping materials were evaluated by three-dimensional simulation. It is found that the NWs located at different positions have different charge injection speeds. And the NW density will strongly affect the charge injection efficiency. The NW at channel center can result in large memory window and acceptable channel controllability. Although the total charges injected into NWs is lower than that injected into NCs under the same programming condition, using NWs as charge trapping material exhibits larger memory window and better channel controllability. It is suggested that the NW is a better choice than NC to be charge storage material from the perspective of memory performance. [Copyright &y& Elsevier]

Effects of oxidation and nitric oxide (NO) post-oxidation annealing (POA) processes on the gate oxide integrity on 4H-SiC are investigated. Interface state density, flatband voltage, electron tunneling barrier height, breakdown field, and time-dependent dielectric breakdown are extracted. With the same NO POA condition, more nitrogen atoms are incorporated into wet oxide than dry oxide. The interface state density can be passivated effectively. At the same time, the electron tunneling barrier height at the SiO 2 /SiC interface approaches the ideal barrier height while positive charges would be introduced in oxide. NO annealing does not affect the breakdown field significantly. Regarding the time-dependent dielectric breakdown (TDDB) reliability, with increasing NO annealing time, the 10-year-projected intrinsic breakdown field decreases. It is concluded that NO annealing is effective in reducing the density of interface traps and hole traps originated from carboxyl defects, but excessive amount of nitrogen will turn into hole traps and thus deteriorates TDDB performance. • With the same NO POA condition, more nitrogen atoms are incorporated into wet oxide than dry oxide. • With nitrogen incorporation, the interface state density can be passivated effectively. • Wet oxidation results in slightly higher breakdown field while NO POA slightly reduces the breakdown field • With increasing NO annealing time, the 10-year-projected intrinsic breakdown field decreases for both wet and dry oxidation samples. • Excessive amount of nitrogen will turn into hole traps and thus deteriorates TDDB reliability of gate oxide on 4H-SiC. [ABSTRACT FROM AUTHOR]

• A well-behaved 4H-SiC PMOSFET device with LOCOSiC isolation structure. • SiC CMOS integrated circuit application. • SiC PMOSFET device behavior and temperature response. • High temperature environment and power electronics application. SiC devices are suitable for high temperature applications due to its' wide energy bandgap and high thermal conductivity. Some SiC CMOSFET ICs have been reported recently. However, less literature address the characteristics of SiC PMOSFET. In this work, we fabricated PMOSFET with Local Oxidation of SiC (LOCOSiC) isolation structure and different gate oxidation processes targeting sub-10V operation. Well behaved PMOSFET with suitable threshold voltage (−5.58 V), low subthreshold swing (200 mV/decade), acceptable hole mobility (3 cm2/V-sec), and low off-state current (<1 × 10−12 A/μm at −10 V) is achieved. Temperature dependence of device characteristics are investigated. These results make the implementation of high-performance CMOS a great progress. [ABSTRACT FROM AUTHOR]

Ge n+/p junctions fabricated by conventional ion implantation (CII) and plasma immersion ion implantation (PIII) are compared in this work. To achieve low junction leakage current, PIII-implanted Ge n+/p junctions require higher annealing temperature to eliminate the Shockley-Read-Hall generation current, which may be contributed to the residual hydrogen and hydrogen-related defects. It is demonstrated that with 500 °C annealing, well-behaved Ge n+/p junction with ultra-shallow junction depth (<50 nm) can be achieved by PIII. With 600 °C annealing, best Ge n+/p junction performance with current on/off ratio ~9 × 105 and ideality factor ~1.07 is achieved by PIII. • Ge n+/p junctions fabricated by conventional ion implantation and plasma immersion ion implantation (PIII) are compared. • The effect of hydrogen atoms on Ge n+/p junction performance is studied. • With 500 °C annealing, well-behaved Ge n+/p junction with ultra-shallow junction depth (<50 nm) can be achieved by PIII. • With 600 °C annealing, Ge n+/p junction with current on/off ratio ~9 × 105 and ideality factor ~1.07 is achieved by PIII. • PIII-implanted Ge n+/p junctions require higher annealing temperature to eliminate the Shockley-Read-Hall generation current. [ABSTRACT FROM AUTHOR]

• LOCOSiC isolation using PAI technology is integrated into the 4H-SiC SBD fabrication. • Smooth topography of LOCOSiC suppresses the leakage induced by field crowding along perimeter. • Thermally grown FOX possessed of better quality sustains higher V BD only with simple field plate termination. In this paper, the local oxidation of SiC (LOCOSiC) isolation using pre-amorphization implantation technology is integrated into the 4H-SiC Schottky barrier didoes (SBD) fabrication to evaluate its isolation ability due to the high sensitivity of SBD to those defects induced by process. Using Ar plasma treatment, the barrier height can be centralized at ~1.1 eV with reduced variation, which lies in between commonly-used SBDs with Ti (1.0 eV) and Ni (1.2 eV), considering cut-in voltage, leakage and breakdown voltage (V BD). Furthermore, at high reverse bias (−200 V), the leakage of the SBDs isolated by LOCOSiC is only ~10−5 A/cm2 at room temperature, 200× lower than that of the SBDs isolated by deposited SiO 2 , because the smoother topography is beneficial to release the field crowding effect. The maximal V BD achieves 515 V only with simple field plate termination. The electric field simulation suggests that the thermally grown field oxide with better quality retards the breakdown at the edge of the metal pad on field oxide. [ABSTRACT FROM AUTHOR]