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A practical exhibition of the consequences of the 3D IC in heat management by adding the fin and heat spreaders to thermal through silicon via (TTSV) and IC respectively is proposed in this paper. Thermal cooling and its distribution of burnt potentials at various conditions are the different possessions which can be simulated using FEM simulator. This paper illustrate materials like Silicon nitride (Si3N4), Aluminium oxide (Al2O3), Silicon dioxide (SiO2) as they have the high thermal conductivity and high temperature capabilities which leads to the thermal management in the 3D IC design. Currently, semiconductor industries has cognizance of the metrics such as low density, high thermal strength, good facture of toughness, excellent wear resistance of Silicon nitride and it also shows better capabilities of high temperature, oxidation resistance and high retention strength compared to other metals. Besides silicon nitride has good resistance to thermal shock due to low coefficient of thermal expansion. Aluminium oxide is known for an better electrical insulator but has high thermal conductivity and which can be utilized as the substrate for integrated circuits. The high temperature furnace insulations and electrical insulations are designed by using the aluminium oxides as it has high boiling points and melting points. This makes the rapid use of alumina films in manufacture of IC industry. The other uses of alumina films include spark plug insulators, micro-electric substrates and insulating heat sinks. Silicon dioxide has the properties which helps to use them as the insulator material in IC technology as it has high thermal stability and making it useful for device integration and has high dielectric strength and thermal expansion coefficient is very low and in this paper we have taken these three materials and these materials have been implemented in our model and advertence the outcomes that which material is working efficiently and preciously.

The evolution of the internet drastically increases the utilization of online data, which needs security using unique identification. The traditional methods of security, such as password, personal identification number (PIN), could not reach the user-friendly requirement of the users. There is a necessity to provide high security for the data by using a unique identification system. Today, in many situations, biometrics plays a crucial role in today’s authentication and recognition. Biometrics deals with unique physical and behavioral characteristics. Fingerprint, face recognition, iris/retinal recognition, voice recognition and vein recognition are some of the biometrics which is used for authentication purpose. In this paper, we highlight different processes that involve finger veins and palm veins recognition and authentication. These finger and palm vein is identified as one of the important unique identifications that can be used for the authentication which provide the security for the important personal data. In this study, we noticed that the advantage of using a vein for the authentication process is that it provides high security because it can be detected even when a finger or palm got injured, and it works only when the person is alive otherwise the authentication fails.

Embedded applications software code is increasingly growing in size. Whereas the entire code of all control panels in a car provided for roughly a few 100 K code lines a decade ago, a single control panel such as the engine control can now have up to 1million code lines. With these help of good approach, common scenarios are developed for other, even for mobiles, embedded systems like PDA’s, cell phones etc. However, increasing software size requires greater memory and can therefore raise the cost of an embedded system considerably. The starting of this pattern was already established in the early 1990 s. The compressed code is created by compressing the binary numbers using a code compression tool (at the time of design) is stored in the instruction memory of the embedded devices. The compressed instructions are decompressed and implemented by the processor at the time of startup. One of the serious challenges is that the tables will become wide in size and therefore decrease the benefits of compressing the code that could be accessed. Although the whole research in this area has mostly concentrated on improving greater code compression without specifically targeting the issue of wide look-up table sizes.

3D Integration technology is probably the best methodologies among others which suits CMOS applications with in various layers of devices are stacked with high thickness interconnects between the layers. In 3D IC structure electrical and thermal models are introduced for the interface between Through-Silicon-Via’s (TSV’s). TSV’s can be used to enable the 3-D platform; however this TSV’s will represent additional concerns. TSV-to-substrate and TSV-to-TSV noise coupling is assessed inside the 3-D IC’s. A vertical TSV’s design is proposed to reduce the area per TSV, capacitive coupling and effective inductance as compared with the other classical design patterns. TSV’s and substrate noise coupling is one of the major drawbacks in 3D IC. Some of the researchers have tried to overcome the problems in TSV based 3D IC due to noise coupling using different models, materials and different circuit techniques. This paper shows the complete road map for the noise coupling reduction in future IC integration.

3D IC Integration shows the most emerging technology for future integration nodes which is now a most important trend for the semiconductor industries. Through-silicon-via (TSV) based integration is the prime technique to facilitate 3D IC integration without compromising the Moore’s law. It is likely to usher the IC industries a paradigm shift from planar integration as it provides major benefits like improvement of system performance, power and enables heterogeneous integration. In this paper, we report Germanium/poly-germanium as an substitute material for Silicon/poly-silicon due to its superior carrier mobility. Mobility of electrons and holes in c-Silicon is 1500 cm2/V-s and 450 cm2/V-s respectively, where as in c-Germanium, the respective values are 3900 cm2/V-s and 1900 cm2/V-s. Therefore, considering these carrier mobility values we can envisage that poly germanium will be one of the ideal candidate towards realizing a high speed TSV interconnect when compared with poly-silicon. Nevertheless, even though copper is used widely to fill TSVs, it is also bereft of proper thermal expansion match with Silicon/dielectric (SiO2). The coefficient of thermal expansion (CTE) of Cu (∼17.5x 10-6 /°C) is many times more than of silicon (∼2.5x 10-6/°C). Hence, there will be heavy mismatch between Cu filled TSV and Silicon/SiO2, and then it creates stress and strain between the interfaces. The CTE of germanium (5.8x 10–6/°C) is very close to Silicon, thus there CTE mismatch is very less, this fact is also an added advantage for Germanium to challenge copper as TSV material.

Three Dimensional IC (3D IC) integration is one of the emerging technology which suits CMOS applications by stacking various IC layers vertically. In 3D IC, IC Layers are interconnected electrically using Through Silicon Vias (TSV’s) and mechanically by Cu–Cu bonding. The major drawbacks in 3D IC structures are thermal issues between layers and noise coupling between TSV-to-substrate and TSV-to-TSV which leads significantly on the overall system performance. This paper presents an extensive survey on one of the major issue in 3D based IC integration technique called thermal issues between the layers and how the researchers have tried to overcome the problems by introducing various materials which are suitable for elimination of hotspot, by introducing spreaders among the layers. This extensive survey work shows the complete roadmap for the thermal management in future IC Integration.

Electrocardiogram (ECG) is widely used technique in study of heart beat irregularities such as cardiac arrhythmias, sinus rhythms and heart failure. It is a significant and popular technique to classify and detect the cardiac infraction. ECG signal analyses the electric activity of heart and outputs it in the form of waveforms which help in detection of heart irregularities. The main goal of this research work is to classify the arrhythmia with more accurate results in less computational time. The research is carried in machine learning technique- SVM classifier using Discrete Wavelet Transform (DWT). In this methodology, ECG samples of three different classes-Normal Sinus Rhythm, Congestive Heart Failure and Cardiac Arrhythmia were collected from MIT-BIH and BIDMC databanks. The collected signals were prepared into training set and testing set with a ratio of 70:30 percent respectively. Total 190 features were extracted from the prepared data using Discrete Wavelet Transform. DWT was chosen as it has the ability to vary the window size depending on the frequency. The extracted features were given to SVM classifier, which is best for classification purpose. The results were evaluated using the testing set and the final results were plotted using a confusion matrix. The performance accuracy of the model is 95.92 percent.

Complementary metal oxide semiconductor (CMOS) devices are expected to face new challenges such as exponential current leakage, DIBL, hot carrier effects, and etc. at nano scale. Hence the CMOS technology is being supplanted by the nanotechnologies. Quantum-dot Cellular Automata (QCA) is key technology at nano scale which operates at tera hertz of speed. Comparing with the traditional CMOS technology, the QCA technology has low power consumption and high density. This technology also has a unique methodology such as “processing in wire” and “memory-in-motion”. This work confers an area proficient, high speed full adder (FA) design with efficient clocking. The proposed full adder design comprises of 26 Quantum cells with delay of two clock phases, area occupancy of 0.03 µm2. This paper utilizes the unique characteristics of QCA and the proposed Wallace tree multiplier is implemented with the mentioned FA and is designed by using QCA Designer 2.0.3 tool.

Through-silicon-via (TSV) technology has emerged as the key technology to enable 3D IC integration. 3D integration is seen as the leading candidate, which can help in sustaining Moore’s Law to future IC technology nodes. It clearly set a benchmark to the IC industry due to its tremendous benefits in performance, data bandwidth, and supports heterogeneous integration. In 3D IC structure TSV’s are used to carry the overall electrical signal between the layers. The major drawback in the TSV based 3D integration is noise coupling between aggressive (electrical signal carrying TSV; ETSV) and victim TSV’s (ground). It can be reduced by creating very good isolation between TSV’s and Si substrate by using different liner materials around TSV’s. In this work, we have addressed various TSV models to reduce noise coupling between the TSV’s. The models we have studied are single layer model and stacked layers of liner model. Apart from this we have studied how the core materials in the TSV reduces noise coupling between aggressive and victim TSV’s. Also, we have shown the high frequency study for proposed models. Finally, our work shows single layer model with Crystalline-Germanium is comparably better noise coupling reduction even at higher frequency.

Thermal through silicon via (TTSV) and heat spreaders plays a vital role in heat management in 3-Dimentional IC integration. However in recent years FIN to TTSV and heat spreaders has proposed to detects and spread heat in any one direction which leads to the damage of an integration circuit (IC). This paper proposes a FIN with optimal directions and heat spreaders to spread the heat in various directions and finally the heat absorb towards heat sink effectively. In this work, we have also demonstrated various thermal cooling effects and its impact on the distribution of potential across IC at different conditions. We have studied these using FEM Simulator for (1) 3D IC architecture with FIN and heat spreaders using Graphene and CNT material, (2) TTSV with FIN and heat spreaders of Graphene, (3) TTSV with fin and heat spreaders of CNT, (4) TTSV with FIN direction towards heat source made of Graphene and CNT, and (5) TTSV with FIN direction towards TSV made of CNT and Graphene. Our result shows that CNT has better thermal cooling management towards heat source as well TSVs than Graphene with order greater than 100 Kelvin.

Semiconductor Industries are mainly facing problems by using planar integration (2D IC) in order to overcome the paradigm shift has been adopted as vertical IC integration so called 3D IC. It not only provides higher bandwidth, higher system performance, but also consumes less power with system scaling. 3D IC has an ability to coordinate IC chips by stacking them vertically and electrically associated utilizing TSV's (Through Silicon Via). By utilizing TSV's in 3D IC, TSV noise coupling is one of the vital factors for the system performance aspects. TSV's play major role in carrying the electrical signal between the IC’s of 3D integrated structures. Noise coupling is the major drawback between the signal carrying TSV’s (ETSV) and victim TSV’s. In this work, we have shown better electrical integrity by reducing the noise coupling from TSV to Silicon substrate by essentially changing the CMOS compatible dielectric materials as liner structures. In addition to this performance of various proposed structures are analyzed and verified under different parameters like electrical signal and at high frequencies. Also, the noise coupling analysis has been studied for Electrical TSV’s (ETSV), TTSV (Thermal Through Silicon Via) and heat source. Finally, our work shows liner material Teflon AF1600 shows comparably better noise coupling performance for all the proposed models even at higher frequencies like THz.

Street extraction from ethereal pictures is fundamental for regular daily existence having a few helpful application in for instance metropolitan arranging and auto route. Streets are right now separated utilizing techniques that requires a great deal of manual work directed by people which is both tedious and blunder inclined. The point of this work is to build up a hearty calculation that can consequently remove streets from elevated pictures. The most appropriate technique for programmed street extraction is an AI approach dependent on stacked convolutional neural organizations. The strategy was executed and considered in contrast to four distinctive street pictures nearby the motorway ORR connecting Hyderabad. The best organization accomplished a review of 0.764, accuracy of 0.812 and nature of 0.670 over a test set of beforehand concealed pictures. Taking into account that the strategy utilized was moderately basic, the outcome is to be viewed as aggressive contrasted with other distributed works.

This work addresses the robot controlled by hand gesture and voice control. In the technology era, the space between the physical and the digital world is brought closer by the introduction of gesture concept. For all the dangerous tasks we prefer technology rather than people. Even though these robots are being controlled manually in the early stages, these can now be controlled via voice and gestures. This technology of gesture and voice recognition can be defined by the interaction between the computer and the body language of human beings. This constructs the communication link between technology and mankind. The target of this work is to upgrade the complete security to the robot and to simplify the controlling mechanism.