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Presently Si-based field-effect transistors (FETs) are approaching their physical limit, and further scaling their gate length down to the sub-10 nm region is becoming extremely difficult. Benefitting from the atomic-scale thickness and dangling-bond-free flat surface, two-dimensional semiconductors (2DSCs) have good electrostatics and carrier transportability. The FETs based on the 2DSC channel have the potential to scale the FETs’ gate length down to the sub-10 nm region while avoiding apparent degradation of the device performance. In this review, we introduce the recent experimental and ab initio quantum transport simulation progress in the 2D FETs with a gate length less than 10 nm. Remarkably, in the extremely optimistic condition, many 2D FETs (i.e phosphorene, silicane, arsenene, tellurene, WSe2, InSe, Bi2O2Se, GeSe, etc.) show excellent device performance for the high performance and/or low power applications and indeed can extend Moore’s law down to 1 ∼ 2-nm gate length in terms of the ab initio quantum transport simulation. The sub-10 nm 2D tunneling FETs are predicted to generally have smaller energy-delay products compared with the 2D metal–oxide–semiconductor FETs and appear more competitive for the low power application. The carrier effective mass plays a key role in determining the device performance. Via negative capacitance techniques, the device performance can be further improved. Finally, we outline the challenges and outlook on the future development directions in the sub-10 nm 2D FETs.

In this paper, a novel third-order autonomous memristor-based chaotic circuit is proposed. The circuit has simple topology and contains only four elements including one linear negative impedance converter-based resistor, one linear capacitor, one linear inductor, and one nonlinear current-controlled memristor. Firstly, the voltage-current characteristic analysis of the memristor emulator for different driving amplitudes and frequencies are presented. With dimensionless system, the symmetry, equilibrium point and its stability are analysed. It is shown that the system has two unstable saddle-foci and one unstable saddle. A set of typical parameters are chosen for the generation of chaotic attractor. Differing from the common period-doubling bifurcation route in smooth dynamical systems, this memristive system shows abrupt transition from the coexisting period-1 limit cycles to robust chaos when varying system parameters. Various dynamical behaviors are analysed using the numerical simulations and circuit verifications.

The gate induced drain leakage (GIDL) effect in negative capacitance (NC) FinFET is investigated. A Landau–Ginzburg–Devonshire equation (which considers the polarization gradient in ferroelectric material) is used to estimate the characteristics of the NC FinFET. Specifically, metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NC FinFETs are compared, in order to figure out the effect of the internal metal layer on the GIDL effect. To analyze the impact of the polarization gradient on the GIDL effect in NC FinFET, a polarization gradient coefficient is varied. For MFMIS, the polarization gradient doesn't significantly affect the device performance. The subthreshold swing improves but the GIDL effect deteriorates because of the “uniform” NC effect in channel region. For MFIS, the device performance is explicitly affected by the polarization gradient. Smaller polarization gradients result in non-uniform NC effect in channel region, resulting in severe GIDL effects. On the other hand, higher polarization gradients alleviate GIDL effects.

Recently, increasing attention has been concentrated on negative permittivity with the development of the emerging metamaterials composed of periodic array structures. However, taking facile preparation into consideration, it is important to achieve negative permittivity behavior based on materials’ intrinsic properties rather than their artificially periodic structures. In this paper, we proposed to fabricate the percolating composites with copper dispersed in epoxy (EP) resin by a polymerization method to realize the negative permittivity behavior. When Cu content in the composites reached to 80 wt%, the conductivity abruptly went up by three orders of magnitudes, suggesting a percolation behavior. Below the percolation threshold, the conductivity spectra conform to Jonscher’s power law; when the Cu/EP composites reached to percolating state, the conductivity gradually reduced in high frequency region due to the skin effect. It is indicated that the conductive mechanism changed from hopping conduction to electron conduction. In addition, the permittivity did not increase monotonously with the increase of Cu content in the vicinity of percolation threshold, due to the presence of leakage current. Meanwhile, the negative permittivity conforming to Drude model was observed above the percolation threshold. Further investigation revealed that there was a constitutive relationship between the permittivity and the reactance. When conductive fillers are slightly above the percolation threshold, the inductive characteristic derived from conductive percolating network leads to the negative permittivity. Such epsilon-negative materials can potentially be applied in novel electrical devices, such as high-power microwave filters, stacked capacitors, negative capacitance field effect transistors and coil-free resonators. In addition, the design strategy based on percolating composites provides an approach to epsilon-negative materials.

Steep slope negative capacitance MOSFETs with HfYOx ferroelectric on FDSOI were experimentally demonstrated. An average SS of 30 mV/dec was achieved over 3 decades of drain current. The negative capacitance is believed to be a transient phenomenon because a strong polarization switching is needed for the steep slope. We found that the sub-thermal SS degrades with the cycling measurements, which is assumed to be caused by the trap charging in the ferroelectric oxide layer. The tradeoff between polarization and charge trapping is responsible for the subthreshold behavior of the device.

Frequency- and mobility-dependent admittance have been observed in organic polymer light-emitting diodes. In this paper, we developed a model to describe this dispersive behavior using a modified Drude theory. In this model, a phase angle difference between the applied electric field and the average displacement of the charge carriers is introduced rather than using a complex mobility. This newly proposed model successfully describes the dispersive nature, as well as the negative capacitance effect, at low frequencies in organic polymers. The simulation results of this model also fit the negative capacitance data reported in the literature, provided that a suitable phase angle difference is given. Keywords: Complex carrier mobility, Dispersive polymers, Drude theory, Negative capacitance, Organic polymer light-emitting diodes

In the current study, the structural, optical, photoelectrical and electrical properties of CdS/Y/CdS thin films are investigated. The current design include the evaporation of a layer of 70 nm thick yttrium between two layers of CdS. Each CdS layer is of thickness of 500 nm. It is observed that the yttrium slab increased the microstrain, defect density, stacking faults and decreased the grain size and redshifts the indirect allowed transitions energy band gap of CdS. In addition an enhancement by ~5 times in the light absorbability is detected at 1.74 eV. The enhanced absorbance results in increasing the photocurrent by ~ 21 times and changed the recombination mechanism from a trap assisted recombination to supralinear recombination mechanisms. Moreover, the ac signal analysis in the frequency domain of 10–1800 MHz has shown that the yttrium forces the CdS to exhibit negative capacitance effect and make it behave as band stop filter with notch frequency of 1520 MHz. The quality of the CdS/Y/CdS films as microwave cavities are screened by the evaluation of the return loss which revealed good features of the nanostructured films as microwave receivers.

Hf1-xZrxO2 films have attracted significant attention for applications in ferroelectric memory and negative capacitance transistors due to their ferroelectric properties and high compatibility to CMOS integration. X-ray photoelectron spectroscopy (XPS) was utilized to characterize the energy band alignments of Hf1-xZrxO2/Si and bandgaps of Hf1-xZrxO2 with different Zr compositions. Results show with the increment of Zr composition in Hf1-xZrxO2 from 0 to 1, the valence band offset ΔEv for Hf1-xZrxO2/Si interfaces increases from 2.09 to 2.94 eV, while the conduction band offset ΔEc decreases from 2.37 to 1.06 eV. This is resulted from the increasing Zr composition leading to a decrement of bandgap and electron affinity in Hf1-xZrxO2. Both ΔEv and ΔEc are all above 1 eV, which is large enough to block electrons and holes for carrier transport in channel regions for the Hf1-xZrxO2 based transistors. The band alignment for Hf0.52Zr0.48O2/Si0.55Ge0.45 was also investigated exhibiting a much larger ΔEv and a slightly lower ΔEc as compared to Hf0.52Zr0.48O2/Si.

Light emitting polymer poly [2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylenevinylene] (MEH-PPV) is blended with a wide bandgap electron transport material benzothiadiazole (BT) and its effect on the electronic properties has been studied by capacitance and impedance spectroscopy (IS) in PLEDs. The impedance data is fitted using equivalent circuit models and the minimum parallel resistance (Rp) at zero bias have been obtained for 1:3 ratio of MEH-PPV:BT blended devices. The negative capacitance (NC) shows the occurrence of the trap-assisted non-radiative recombination mechanism at low frequencies in the unblended MEH-PPV PLEDs. Further, this behavior is seen to be reduced in PLEDs with MEH-PPV:BT blends. This clearly suggests that the blending of MEH-PPV and BT at different weight ratios results in the suppression of trap-assisted recombination. This can be attributed to the elimination of trap states due to the dilution of semiconductor material on account of the addition of wide bandgap host material. Moreover, the blended devices have shown a significant improvement in the conductivity at small bias voltages.

In this letter, we investigated negative capacitance (NC) effect in nanocomposite based quantum dot sensitized solar cells. TiO2 and graphene-TiO2 nanocomposite photoanode based on quantum dot sensitized solar cells (QDSSCs) were fabricated and the capacitance-voltage (C–V), capacitance-frequency (C-f) and conductance-voltage (G/ω-V) characteristics were studied by attention the series resistance (Rs) effect. Admittance spectroscopy of QDSSCs were measured in a variable voltage and frequency ranges of (−2 V) - (+2 V) and 10 kHz-10 MHz, respectively. Capacitance values are exhibited a behavior transition from the positive to negative value after 50 kHz. As the capacitance values decreases, conductance increases in the NC region. Negative capacitance effect of meaning that QDSSC indicates an inductive behavior. Inductive behavior, which means that electrons injects from fluorine-doped tin oxide (FTO) conductive glass electrode to photoanode (graphene-TiO2). Also, NC phenomenon has not form significant effect on Rs.

Negative capacitance (NC) phenomena is recently suggested as a breakthrough that can lead to the improved transistor by decreasing the subthreshold swing. To understand the NC phenomena, we investigated the effects of the ferroelectric properties such as the remnant polarization depending on the switching cycles in Si-doped HfO2 thin film capacitor. The ferroelectric properties were controlled by using the wake-up effect, in which the remnant polarization enhances as the number of switching cycles increase. The relation between the wake-up effect and the voltage drop region with the negative differential capacitance were elucidated. The dynamic hysteresis loops were fitted based on Landau-Khalatnikov equation, and the free energy as a function of polarization was obtained. The Landau coefficients showed that the double-well feature of the free energy becomes more apparent due to the wake-up. Based on the wake-up effect on NC phenomena, we show that the NC phenomena is well described by Landau-Ginzburg theory of ferroelectrics.

Wave propagation control in piezoelectric meta-structures has been developed in recent years, which focuses on coupling proper electric media via piezoelectric materials for elastic wave filtering properties within a low frequency range. In order to develop broadband band gaps and diversified wave propagation characteristics of mechanical meta-structures for different complex practical applications, the research proposes an innovative piezoelectric beam meta-structure using electronic negative capacitance dual-adjacent/staggered electrical connections. In the proposed meta-structures, a unit periodic cell composed of four adjacent primitive periodic cells (including four piezoelectric patches with different polarization directions) are connected to negative capacitance circuit shunts using electrical dual-adjacent/staggered patterns. Based on the Timoshenko beam theory and wave propagation theory, a theoretical modeling of the proposed meta-structure is established for evaluating wave propagation properties. Furthermore, wave attenuation performance of the proposed structure is investigated and compared with the traditional meta-structure with negative capacitance independent electronic networks in which negative capacitance shunts are independently applied to single piezoelectric patch or bimorph piezoelectric patches within a unit primitive periodic cell. Results show that the proposed innovative meta-structure utilizes less negative capacitance shunts for achieving better wave attenuation performance, and has more stable negative capacitance control system in practical applications.

In this study, a metal-insulator-semiconductor (MIS) type Schottky barrier diodes (SBDs) were fabricated by growing a thin Al2O3 insulator layer between Au/Ti and n-GaAs using atomic layer deposition (ALD) method. The effect of temperature and voltage on interface states (N-ss) and series resistance (R-s) of the (Au/Ti)/Al2O3/n-GaAs (MIS) type Schottky barrier diodes (SBDs) was investigated using the capacitance/conductance-voltage (C/ (G/omega-V) data measured in wide range of temperature (200-380 K) and voltage (+/- 5 V). It was found that C and G/omega are strongly dependent on temperature and voltage. The value of C in the forward bias region reaches to maximum and then becomes negative. This negative capacitance (NC) behavior of this SBD is observed for each temperature level. Also, capacitance-current (C-I) and conductance-current (G/omega-I) plots were drawn to explain the NC behavior. The negative value of C in the accumulation region corresponds to the maximum value of G/omega. Such behavior of C can be explained by the loss of interface charges located at (Al2O3)/n-GaAs interface because of impact ionization process, the existence of surface states (N-ss), series resistance (R-s) and interfacial of (Al2O3) oxide layer.Therefore, the voltage dependent profiles of R-s and N-ss were obtained using Nicollian-Brews and Hill-Colleman methods for enough high forward biases as a function of temperature at various positive bias voltages. The changes in R-s and N-ss values were attributed to restructure and reordering of the carriers under temperature and voltage effects.

Various researchers have investigated the behavior of a linear mechanical oscillator coupled to a nonlinear mechanical attachment that has essential stiffness nonlinearity. Under certain conditions, the essentially nonlinear attachment acts as a nonlinear energy sink (NES) and one-way energy transfer from the main structure to the nonlinear attachment can be achieved. An important characteristic of an essentially nonlinear attachment is that it does not posses any preferential resonance frequency, resulting in increased robustness against detuning, thereby enabling frequency-wise wideband performance. This work presents an experimentally validated piezoelectric-based NES for wideband vibration attenuation. The electrical circuit consists of a negative capacitance shunt (introduced for cancelling the piezoelectric capacitance) combined in series with a nonlinear capacitance of cubic order that is realized using operational amplifiers. Design and practical implementation of the NES shunt circuit are discussed in detail. The performance of the piezoelectric NES to attenuate vibrations over a wide range of frequencies is numerically simulated and experimentally validated for a cantilever in the absence and presence of tip mass attachments.

The capacitance of magnetic tunnel junctions (MTJs) with the tunneling magnetocapacitance (TMC) effect has drawn lots of attention but there is still a lack of research on the capacitance anisotropy. In this work, a study of the capacitance in MgO-based MTJ is performed. The negative capacitance is observed and indicates the importance of interface capacitance in the MTJ. In further research, the interface capacitance depends on the relative orientation of magnetization in the two ferromagnetic layers (FMs), exhibiting a strong anisotropy. The Debye-Frohlich model combined with the magnetization dependence of relaxation time is introduced to explain the behavior. Theory and experiment results of the relaxation time as a function of the relative angle of the two FM magnetizations are well fitted. It reveals that the TMC originates from the interface charge accumulation and spin-dependent tunneling. All the results suggest that the interface capacitance with apparent anisotropy plays an essential role in the TMC.

Although ferroelectric material is highlighted for its negative capacitance (NC) effect integrated into MoS2 devices, it usually needs a dielectric layer to provide positive capacitance, which is not conducive to scaling down of transistors. In this work, a monolayer Al1-xZrxOy is used as the gate dielectric to fabricate back-gated MoS2 negative-capacitance FETs (NCFETs), in which host Al2O3 exhibits a positive capacitance and the embedded ZrO2 crystals formed through rapid thermal anneal at 550℃ exhibit a NC effect. By optimizing the Zr content in the Al1-xZrxOy thin film, an enhanced ferroelectricity and a reasonable match between the negative capacitance and the positive capacitance have been achieved for the Al0.93Zr0.07Oy thin film, resulting in excellent device performances: small subthreshold swing (SS) of 28 mV/dec and high on/off current ratio of 6.4 × 107. Moreover, after the Al0.93Zr0.07Oy thin film is suffered from a remote NH3-plasma treatment, its ferroelectricity and NC effect are further enhanced due to the reduction of oxygen vacancies and the improvement of interface quality, thus boosting the performance of the relevant NCFET: the SS is lowered to 18 mV/dec, where the sub-60 mV/dec SS spans almost three orders of Id (drain current) magnitude, the hysteresis is reduced to 25 mV and the driving current is 30% higher than that of the untreated sample. Therefore, the Al0.93Zr0.07Oy thin film with the NH3-plasma treatment as the gate dielectric of MoS2 NCFET has a great potential in achieving the steep-slope, free-hysteresis and low power-consumption performances.

The negative capacitance is a peculiar phenomenon frequently observed in electrochemical impedance spectroscopy (EIS) measurement for perovskite solar cells (PSCs). However, the origin and mechanism of the negative capacitance in PSCs remains ambiguous. Here, planar PSCs with different electron transport layer (ETL) strategies (SnO 2, TiO2, or without ETL) were characterized by EIS in a wide range of frequencies under various conditions. The negative capacitance solely occurred in the moderate frequency region as the perovskite layer directly contacted with the conductive SnO2: F (FTO) substrate under illumination and open-circuit conditions. Based on semiconductor band theory, the origin of negative capacitance to the formation of an inversion layer in the perovskite/FTO interface induced by the interfacial energy band over-bent under illumination and open-circuit conditions. Our study provides important insight into the physical mechanism behind the negative capacitance of PSCs.

Among various strategies developed for the attenuation of noise and vibration in mechanical structures, piezoelectric shunt damping, which consists in connecting piezoelectric transducers integrated in a structure to electric or electronic circuits, is a promising alternative for use in small- and mid-scale structural components. Despite the fact that the shunt damping technology has been investigated for quite a long time, it is recognized that its application to real-world structures still requires developments aiming at improving its effectiveness and range of application under unavoidable practical constraints. As a result, research on improved solutions related to piezoelectric shunt damping is still very active. Due to the very nature of the piezoelectric shunt damping, it becomes clear that further improvements must consider both mechanical and electrical/electronic aspects. Based on the current state-of-the-art, this paper provides a systematic literature review of different piezoelectric shunt damping strategies developed for the attenuation of vibration and noise in mechanical systems, including an assessment of the basic principles underlying the electromechanical behavior, as well as design procedures and numerical modeling of piezoelectric shunt damping devices applied to elastic vibrating systems. Emphasis is placed on the various types of shunt circuits, including the traditional passive resonant circuits, multimode resonant circuits, adaptive tuning circuits, switching circuits, and negative capacitance. The strategies for location and shape of the piezoelectric transducers is also discussed. A variety of applications recently reported in the scientific literature and in patents are presented. An assessment is made about more significant recent achievements and technological issues to be faced in further developments.

Rapid advances in information technology rely on large capacity, high speed, and thermally stable phase-change nonvolatile materials. This work is investigating the capacitance-voltage characteristics of multinary chalcogenides (Ge15Sb80Se5 and Ge15Sb70Se10In5) to study their electrical properties and their reliant on frequency, bias voltage, and temperature. The results show different capacitance behavior for the two films, Ge15Sb80Se5 and Ge15Sb70Se10In5. Adding indium to Ge-Sb-Se alloy improved its thermal stability by increasing the crystallization temperature by almost 20 K, and shows a fast crystallization process. The results illustrate that the capacitance of Ge15Sb70Se10In5 film has a nonlinear-temperature behavior and becomes negative at high temperatures. The negative capacitance could be attributed to a significant increase in the conductivity of the film due to temperature and applied bias voltage. Moreover, during the phase change, the amorphous-crystalline interfaces might behave as a junction with a potential barrier where charge carriers accumulate. The nonlinearity in the capacitance and conductance is attributed to the nucleation-growth mechanism when the temperature becomes close to the amorphous–crystalline transition temperature (Tc).

Recent studies have shown that organic-inorganic hybrid perovskites (OIHPs) exhibit unprecedented optoelectronic properties for photovoltaic applications. Complete realizations of photo- and electrically induced surface polarization and recombination are critically important for extensively upgrading solar cell performance. We have explored such effects in a planar solar cell comprising ITO(glass)/PEDOT:PSS/CH3NH3PbI3-xClx/PC60BM/PEI/Ag with a maximum power conversion efficiency (PCE) of 15.4%. A remarkable frequency-dependence of surface polarization was observed for the operating device under illumination (i.e. short-circuit current J s c condition) and at steady state (i.e. open-circuit voltage V o c condition). A sign reversal of the capacitance (i.e. negative capacitance) associated with the surface polarization and recombination was detected at some specific steady states. Based on capacitance-voltage (C-V) spectroscopic measurements and theoretical fittings, they can be understood that, (i) a naturally formed surface depletion region due to energy mismatch can be fully suppressed at a very low fluence and moderate forward bias voltage; (ii) a surface capacitance ( C s ) appears at lower ac-modulation frequencies only; (iii) remarkable trap-assist and band to band surface recombination may play the dominant roles for generating the negative capacitive effect in the CH3NH3PbI3-xClx based photovoltaic system.

In this work, the effect of glass/Ge and Au/Ge substrate on the structural, optical and electrical properties of the GaSe thin films is investigated by means of X-ray diffraction, ultraviolet-visible light spectrophotometry and impedance spectroscopy techniques, respectively. While the glass/Ge, glass/GaSe and glass/Ge/GaSe are observed to exhibit amorphous nature of structure, the Au/Ge, and Au/Ge/GaSe are of polycrystalline nature. The formation of the Ge/GaSe interface exhibited high conduction band offset of value of ∼0.90 eV and enhanced the light absorbability of GaSe at 1.47 eV by 80 times. In addition, the modeling of the dielectric spectra for the Ge/GaSe interface revealed optical conductivity parameters presented by scattering time at femtosecond level and improvement of the drift mobility. Moreover, the impedance spectroscopy measurements have shown that with the increasing frequency, the Au/Ge/GaSe/Yb interface exhibit increasing trend of variation in the resistance causing high impedance mode associated with negative capacitance values below 1300 MHz. The effect is completely reversed in the higher range of frequency. These features of the Ge/GaSe interface nominate it as plasmonic interface, microwave cavities and as voltage amplifiers in low power nanoscale devices.

New five grounded immittance function simulators are proposed in this paper. The first one is a positive lossless grounded inductor simulator which employs just one inverting buffer plus-type second-generation current conveyor while the other four proposed circuits include only one non-inverting current feedback operational amplifier. The second and third ones are negative lossless grounded inductor simulators. The fourth one is a positive inductor with a series positive resistor while the last one is a negative capacitance multiplier. All of the proposed circuits except the first one consist of only grounded capacitor(s). However, all of the proposed circuits need a single passive component matching condition. A band-pass filter composed of the first proposed circuit is given as an example. Also, frequency dependent non-ideal gain effects on the performance of all the circuits are given. The results of a lot of SPICE simulations are carried out by using 0.13 µm IBM technology parameters where ± 0.75 V DC symmetrical power supply voltages are utilized. In order to demonstrate the performance of the first proposed circuit, an experimental result is given as an example. © 2018 Elsevier GmbH

The dielectric layer in the sandwich structural device plays a very important role in determining the electrical properties of the ferroelectric film. In this paper, we investigate the effect of the dielectric layers with different thicknesses on switching performance of ferroelectric P(VDF-TrFE) thin films. The hysteresis loops become slanting with increasing thickness of the dielectric layer. A negative slope of the ‘real’ hysteresis loop is apparently observed which demonstrates negative capacitance effect caused by the dielectric layer. This behavior is simulated qualitatively by the Weiss mean field model considering an interfacial dielectric layer in series with a ferroelectric layer. The agreement between experiments and simulations supports that negative capacitance results from the positive feedback among electric dipoles. Furthermore, the switching time of the ferroelectric film increases with the increase of dielectric layer thickness. This study shows that the ferroelectric sandwich structure provides great potential towards low power negative capacitance devices.

Owing to the performance of the CdSe as an optoelectronic material used for the production of quantum dots, photosensors and wave traps we here, in this article, report the enhancements in structural and electrical properties that arises from the nanosandwiching of a 40 nm thick Yb film between two films of CdSe (CYbC-40). The CdSe films which were deposited onto glass, Yb and Au substrates are characterized by X-ray diffraction, temperature dependent electrical conductivity and impedance spectroscopy measurements in the frequency range of 10–1800 MHz. The analysis of the XRD patterns have shown that the glass/CdSe/Yb/CdSe films exhibit larger grain size and lower strain, defect density and lower stacking faults compared to the not sandwiched CdSe. In addition, it was observed that the Yb shifts the donor states of the n-type CdSe from 0.44 to 0.29 eV leading to a modification in the built in voltage of the material. On the other hand, the design of the energy band diagram has shown the ability of the formation of the Au/CYbC-40/Yb as Schottky (SB) and the Au/CYbC-40/Au as back to back Schottky barriers (BBSB). While the SB device show low band pass filter characteristics, the BBSB device performed as band stop filters. The BBSB device exhibited negative capacitance effects with filtering features that reveal a return loss of 42 dB at ∼1440 MHz.

The Au/Pyronin-Y/p-Si/Al Schottky diode was designed and studied by using the DC and AC measurements. Current-voltage (I-V), capacitance-voltage (C-V) and conductance-voltage methods under different frequencies and voltage biasing were measured at room temperature. The I-V characteristics and C-V characteristics were determined by using the electrical and impedance measurements. From I-V characteristics curve, the Au/pyronin-Y/p-Si/Al Schottky diode has a rectifying behavior. The parameters of Schottky diode such as the series resistance, ideality factor, and barrier height were computed for Au/Pyronin-Y/p-Si/Al junction diode. The performance of the Au/pyronin-Y/p-Si/Al diode is attributed to the creation of the interfacial layer by the organic semiconductor dye. Admittance spectroscopy method can describe the series resistance-voltage (Rs-V) and impedance-voltage (Z-V), capacitance-voltage (C-V) and conductance-voltage (G-V) measurements at different frequencies at room temperature. This device showed a negative capacitance at higher frequencies. The origin of negative capacitance is attributed to the inductive behavior of the studied materials. From C-V analysis, different parameters were calculated and analyzed such as the doping concentration, the built-in potential, the depletion layer and the diffusing potential at zero bias. The obtained results support that the electronic properties of the silicon-based Schottky diode can be controlled by the interlayer organic layer (Pyronin-Y).

In this work, a comprehensive drain current model has been developed for long channel Negative Capacitance Germanium Double Gate p-type Field Effect Transistor (NCGe-DG-pFET) by using 1-D Poisson's equation and Landau-Khalatnikov equation. The model takes into account interface trap charges and by using the derived model various parameters such as surface potential, gain, gate capacitance, subthreshold swing, drain current, transconductance, output conductance and Ion/Ioff ratio have been obtained and it is demonstrated that by incorporating ferroelectric material as gate insulator with Ge-channel, subthreshold swing values less than 60 mV/dec can be achieved along with improved gate controllability and current drivability. Further, to critically analyze the advantages offered by NCGe-DG-pFET, a detailed comparison has been done with Germanium Double Gate p-type Field Effect Transistor (Ge-DG-pFET) and it is shown that NCGe-DG-pFET exhibits high gain, enhanced transport efficiency in channel, very less or negligible degradation in device characteristics due to interface trap charges as compared to Ge-DG-pFET. The analytical results so obtained show good agreement with simulated results obtained from Silvaco ATLAS TCAD tool.

A novel voltage-mode (VM) universal filter is proposed in this work. A voltage follower (VF) and a negative impedance converter (NIC) which are two terminal active elements are used in the implementation of the proposed filter. Also, two capacitors and three resistors are employed in the proposed filter as passive circuit elements. On the other hand, each of the VF and NIC can be easily constructed by using a plus-type second-generation current conveyor. One of the main advantages of the proposed filter is the feature of low output impedance resulting in easy cascadability with other VM circuits. Moreover, the quality factor of the proposed filter can be easily adjusted by changing value of only one of the resistors without disturbing its angular resonance frequency. Nonetheless, it requires a single resistive matching condition for proper circuit operation and a unity gain inverting amplifier for only all-pass filter responses. A number of simulation results are achieved by using 0.13 µm IBM CMOS technology parameters with ±0.75 V DC power supply voltages. Power consumption of the proposed filter is approximately found as 3.65 mW through SPICE simulations. Furthermore, experimental test results are included to confirm the theory. © 2018 Elsevier GmbH

The channel doping effects in negative capacitance field-effect transistors (NCFETs) of the metal-ferroelectric-insulator-semiconductor (MFIS) structure are analysed in this work, and an analytical model is developed. The NCFET threshold voltage with channel doping is defined, and a nonmonotonic dependence on the doping concentrations is predicted. A unified charge formulation is developed for the current–voltage characteristics of double gate MFIS structures. Statistical modelling for NCFETs is further developed. Standard deviations of four parameters are extracted, reproducing the distributions of NCFET current–voltage characteristics. Experimental calibrated TCAD simulations validate the analytical model for wide ranges of device parameters, allowing its application to devices and circuits.

The impact of negative capacitance (NC) of the ferroelectric materials in controlling the direct source to drain tunneling (DSDT) in ultra-short channel FETs is presented in this paper. Besides, an analytical model is developed by solving 2-D Poisson’s equation incorporating the degeneracy of source/drain (S/D) regions. We demonstrate that in NC gate stack based Si channel FETs (NC-FETs), the scaling limit can be pushed down to 7 nm gate length, without using effective mass engineering and alternate channel materials. However, under severe subthreshold tunneling circumstances, we find that as the % content of tunneling current rises above the value of 50% in the net current, the subthreshold slope (SS) ceases to improve with the higher ferroelectric thickness. The rigorous analysis of DSDT-Negative drain induced barrier lowering (NDIBL) and impact of the S/D doping over DSDT is also incorporated in the paper. It is found that DSDT decreases drastically in the NCFET compared to baseline FETs due to the NC effect. Hence, using NC effect, transistor can be scaled down to 7 nm physical gate length with SS 80 mV/dec and I OFF 70 nA / μ m compared to 173 mV/dec and 1.5 × 10 6 nA / μ m, respectively for the baseline FET at the same gate length.

This paper reports the evidence of the tunable sub-wavelength topological interface state in local resonance piezoelectric metamaterials . An elastic beam serves as the host medium with periodically arranged local resonators and attached piezoelectric layers. Thus, the shunt circuits connected with the piezoelectric layers can easily change the electromechanical stiffness in any unit cell. By inspired the band-folding mechanism, doubling the primitive unit cell generates two Dirac points, whose one lower point falls below the locally resonant bandgap and is in the sub-wavelength region. Then, employing the shunt circuit’s tunability opens band-folding points to develop two bandgaps associated with the Bragg scattering effect. Band inversion and topological transition exist during the negative capacitance parameter variation. Numerical simulations demonstrate interface wave propagation for excitation at the interface frequency in the heterostructure , composted of two media with different topological invariants. With the assistance of the piezoelectric shunting circuit, our proposed design can induce wave localization over multiple frequency bands, which has potential for applications such as signal filters, energy harvesting and vibration isolation . Finally, we investigate the relationship between the interface frequency and capacitance and consider the local resonance effect on topological interface modes.

For the first time, we analyse SRAM cells made of ferroelectric based negative capacitance (NC) FinFETs considering both global and local variability via Monte-Carlo circuit simulations. First we compare and explain the impact of variability on the device characteristics and the extracted figures of merit of conventional and NC transistors. Then we show that suppressed relative variability in NCFETs leads to lowering of the static Vmin (minimum supply voltage needed for SRAM operation) compared to conventional FinFET based SRAM. We use a physics based compact model for negative capacitance FinFETs realized by a self-consistent coupling of the standard BSIM-CMG compact model for FinFETs with the Landau-Khalatnikov (L-K) model of ferroelectrics. We demonstrate that on including the variability in the ferroelectric thickness and material parameters as well, the advantage of NCFETs diminishes. For the baseline FinFET, we have used model cards from a freely available predictive process design kit (PDK) for the 7 nm technology node where the parameters are optimized for SRAM applications.

In this study, a SPICE model for Negative Capacitance FinFET (NC-FinFET) based on the BSIM-CMG model and Landau-Khalatnikov (L-K) equation is developed. The areas of the ferroelectric layer (AFE) and the work functions (WFs) of n-NC-FinFET and p-NC-FinFET are adjusted to reduce the shift of the threshold voltage. As a result, the NC-FinFET-based seven-stage ring oscillator (RO) has a smaller delay, and energy can down to 72.2 % compared with the FinFET-based RO under the same delay. Furthermore, the NC-FinFET-based 6T SRAM has a smaller read and write time and lower static power than the FinFET-based 6T SRAM. Besides, under two key parameters (the length of the gate (Lg), the width of gate (Wfin), of NC-FinFET), the NC-FinFET-based 6T SRAM has great advantages in static power, read and write time. Therefore, the research on NC-FinFET from the device to the circuit can provide meaningful guidance for the further application of NC-FinFET.

Continuous downscaling of CMOS technology at the nanometer scale with conventional MOSFETs leads to short channel effects (SCE), increased subthreshold slope (SS), and leakage current, degrading the performance of ICs. We proposed a dual-source vertical tunnel field-effect transistor (TFET) with a steeper subthreshold swing (SS) and superior electrostatic control thanks to quantum mechanical band-to-band tunneling. We show that the use of GaSb/InGaAsSb/InAs heterostructure boosts the band-to-band tunneling rate in TFETs, resulting in higher on-state current. Incorporating the negative capacitance effect using ferroelectric materials further enhances the performance of the proposed device greatly. The lowest SS of 21.94 mV/dec and an on–off current ratio of 4.3267 × 1011 were obtained for dual source GaSb/InGaAsSb/InAs heterostructure based vertical TFET. The lowest subthreshold swing was found as 17.37 mV/dec after integrating Hf1–xZrxO2 ferroelectric material into the gate stack. The negative capacitance effect also increases the on-state current tenfold, resulting in an incredible ION/IOFF ratio of 1012. The suggested device focuses on low power consumption applications by assuring a very low leakage current and a reduced subthreshold swing.

We report on the negative capacitance effect in TiO2 films and its relation to charge trapping. We demonstrate that by increasing temperature, it is possible to suppress this effect. This phenomenon is studied for other high-k materials through a simple protocol which allows to control capacitance change with frequency. Indeed, the application of a bias stress increases the charge trapping. This compensates the polarization, and the capacitance reaches negative values. Results are correlated to the density functional theory within the Drude formalism. The work concerns the ability to control the NC for the field effect transistors applications.

Power consumption is the major concern for conventional CMOS based integrated circuit and systems. Since there is a scope of lowering supply voltage with steep-subthreshold swing field effect transistor (FET) devices, it has been advocated as a suitable candidate for future highly energy-efficient circuits and systems. Among all the developed and proposed low power FET devices, that possess subthreshold swing (SS) lesser than 60 mV/decade, the negative-capacitance FETs (NCFETs) have gained the major attention of scientific and academic communities. The concept of negative capacitance (NC) in FET is basically belongs to the amplify the internal potential without modification of transport phenomena. With this capability, the NCFET have achieved similar switching at lower supply voltage, V D D as compared to conventional MOSFETs. Property of achieving similar on-current ( I O N ) lower off-current ( I O F F ) at lower supply voltage indicates that NCFETs help to reduce the power consumption and switching voltage. This can be achieved by slight modification of conventional CMOS devices by adding thin layer of ferroelectric (FE) layer in gate stack. This slight modification in conventional MOSFET is for the NC, which is a special feature of FE materials. FE materials having nonlinear dielectric behavior. This material has preexisting, which is switched in reverse direction when an external electric field is applied. In this paper, a detailed review of NCFET device has discussed and also compared with the Tunnel FET (TFET) and conventional MOSFET.

Recently, a new type of metasurface namely coding metasurface has emerged as a new technology in manipulating waves. Based on its R-bit, a coding metasurface utilizes 2R of coding units to achieve real-time wave controls which makes the operation of a metasurface easier. Although coding metasurfaces have simpler configurations than conventional metasurfaces, it is yet unavoidable to have structural reconfiguration of metasurface in order to perform different functionalities in single or different frequencies. To overcome this drawback, a functionally switchable 3-bit active coding elastic metasurface comprised of stacked piezoelectric patches shunted with negative capacitance circuit is proposed to manipulate elastic longitudinal waves. By tuning the negative capacitance in the circuitry element, arbitrary tuning of stiffness can be attained which leads to the coverage of full 2π phase range without modifying the structure of metasurface. In addition, analytical model and numerical simulations are developed to verify capability of the proposed coding metasurface for covering full 2π phase shift besides having high transmission at the same time. By utilizing the 8 fundamental coding units with different phase response, the proposed metasurface is designed and simulated based on a finite element approach to illustrate switchable functionalities such as arbitrary refraction and wave focusing, which can be realized through proper tuning of the negative capacitance, in broadband frequencies.

This paper, numerically assesses the analog/RF performance of nanoscale negative capacitance junctionless carbon nanotube field-effect transistor (NCJL-CNTFET). The simulation study is based on the non-equilibrium Green's function (NEGF) formalism in conjunction with the self-consistent device electrostatics, including the Landau–Khalatnikov (L-K) equation and the ballistic transport conditions. The proposed nanoscale analog transistor is endowed with four multi-objective improvement assets, namely, gate-all-around (GAA) configuration for the best gate control, metal-ferroelectric-metal-insulator-semiconductor (MFMIS) gating structure for boosting the device performance via the NC feature, junctionless paradigm for simplifying the fabrication processes, and the carbon nanotube-based channel due to its exploitable transport benefits. The quantum simulation study investigates the transfer and output characteristics, transconductance, drain conductance, transconductance efficiency, gate capacitance, and cut-off frequency. We have also studied and analyzed the impact of ferroelectric thickness on the device figures of merit. The NCJL-CNTFET have exhibited several distinctive behaviors, namely, shift in threshold voltage , negative differential resistance, and negative conductance. Moreover, it has been found that utilizing the NC paradigm can significantly boost the performance of the JL-CNTFET in terms of transconductance, gate capacitance, and transconductance efficiency. Our encouraging results make the studied NCJL-CNTFET a promising candidate for high-performance and low-power analog/RF applications.

Negative Capacitance Field-Effect Transistor (NC-FET) is one of the emerging technology for the future ultra-low power circuits. NC-FET incorporates a ferroelectric layer within the transistor gate stack, which provides an internal voltage amplification. However, Negative Differential Resistance (NDR), which occurs at thick ferroelectric can deteriorate NC-FET devices in which the drain current, in the saturation region, decreases with drain voltage increase. This noticeably harms the figure of merits of circuits, especially when it comes to analog applications. This work presents a detailed analysis on the correlation between ferroelectric thickness and NDR effects using well-calibrated TCAD infrastructure for 14 nm FDSOI. For the first time, a novel extension length modulation technique is proposed to mitigate NDR effects effectively. Our technique allows designers to optimize the combination of ferroelectric thickness and extension length in which NDR effects are well suppressed, thereby maximizing the performance and gain of analog circuits.

In this paper, we study the multi-domain switching dynamics for a metal–ferroelectric–insulator–semiconductor (MFIS) type negative capacitance Fin Field Effect Transistor (NC-FinFET) for a 10 nm technology node. To study its characteristics, we develop a SPICE model for multi-domain NC-FinFET. Our proposed model is based on Feynman’s pedagogical model of microscopic origin of ferroelectricity. We develop this model using the positive feedback mechanism for dipole–dipole interactions in the ferroelectric material in conjugation with the BSIM-CMG model for the underneath FinFETs. This study reveals that the drain current achieved in a multi-domain case is lower than the mono-domain case. The negative differential resistance (NDR) effect in transistor characteristics is more pronounced in multi-domain NC-FinFET compared to the mono-domain case. Increasing variation in individual domain parameters of the ferroelectric material i.e., coercive voltage ( V C ) and remnant polarization ( P R ), further lowers the drain current with a hysteresis in the drain current characteristics in the multi-domain NC-FinFET.

– In this work, we have investigated electron transport across Galfenol (FexGa1-x) and Nickel-based Schottky contacts deposited onto n-Si substrates using conventional DC current-voltage (I–V) measurements and have uniquely studied the effects of improper back contact causing additional bias dependent Resistance-capacitance (R–C) components using AC Impedance spectroscopy by choosing proper equivalent circuit models. Junction barrier height and ideality factor were obtained from DC current-voltage characteristics, and bias dependent impedance measurements have been carried out. From Impedance spectroscopy analysis the magnitudes of depletion layer capacitance and barrier height have been calculated and have been compared for both the junctions, and the effect of additional components has been distinguished. Negative capacitance behaviour at lower frequencies and higher forward bias regime has been observed, which might be attributed to interface states in presence of injected charge carriers and by choosing an equivalent circuit having inductor-resistor (R-L) type relaxation, better fit of experimental Nyquist plots of FeGa Schottky junction have been achieved.

We present a TCAD simulation of the negative capacitance gate-all-around (NCGAA) field-effect transistor with the 3-D Ginzburg-Landau-Khalatnikov Model. The baseline device is based on the 2020 IRDS Table, and the mobility model is calibrated to account for ballistic transport and to match the “1.5 nm node” IRDS on-current requirement. The NC parameters are extracted from experimental C-V data. The NC-GAA shows reduction in the off current by one order of magnitude and a 40% on-current boost. If the gate work function is shifted to align the NC-GAA’s off-current with the IRDS high performance requirement, it is shown that NC-GAA can achieve the on-current and VDD requirement of every node through the “0.7 eq node,” which is the last node predicted in the 2020 IRDS Table. Furthermore, NC-GAA can even achieve a “0.5 eq node,” which is three additional nodes beyond the baseline “1.5 nm node.” We also show that these benefits are retained over a varying set of ferroelectric parameters.

In this study, negative DIBL (NDIBL) due to negative capacitance is used to improve MOSFETs and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) circuits by employing custom-built Simulation Program with Integrated Circuit Emphasis (SPICE) model. A multi-threshold technique was proposed by using NDIBL effect, and it can be manufactured by simple manufacturing process without increasing footprint of transistor. The influence of the negative DIBL effect of a negative capacitance field-effect-transistor (NCFET) on transistor effective drive current (Ieff) and CMOS circuit performance were analyzed. The results shown that increasing NDIBL effect increased Ieff by ~12%. A 7-stage ring oscillator (RO) was simulated to analyze the CMOS circuit energy-delay, and it shown that significant delay reduction, at iso-energy and iso-area, can be achieved owing to NDIBL effect of NCFET. A 6T Static Random-Access Memory (SRAM) cell was investigated, and enhanced hold and read static noise margins (SNM) are achieved owing to NDIBL effect. Moreover, several methods of increasing NDIBL effect were proposed.

In this paper, ferroelectric material based Dual Material Gate-Doping Less Tunnel Field Effect Transistor (DMG-DLTFET) is designed using gate stacked PZT to induce negative capacitance (NC) in the device and analyzed for various device parameters namely trans-conductance (gm), drain current (Id), subthreshold slope (SS), threshold voltage (VTH) and Total capacitance (CT). Simulated parameters are compared with conventional DMG-DLTFET and it has been found that NC based DMG-DLTFET gives better results. Furthermore, NC reduces the SS resulting in fast switching and hence low power consumption. The effect of thickness of the dielectric material PZT is presented which plays vital role in deciding negative capacitance in device.

With the rapid development of semiconductor process, both tunneling field effect transistor (TFET) and negative capacitance field effect transistor (NCFET) are regarded as the effective low power devices. In this paper, a novel silicon-based dual source U-shaped channel TFET with negative capacitance (NCDU-TFET) is proposed and investigated by Synopsys Sentaurus TCAD. We pick ferroelectric material (Hf0.5Zr0.5O2) as the gate dielectric. The higher electric field caused by negative capacitance effectively increases the tunneling rate, so the super-steep subthreshold swing (SS) and higher on-state current are obtained for NCDU-TFET. Besides, the impacts of device parameters including gate dielectric layer thickness, coercive electric field and remnant polarization are also analyzed systematically in this paper. The simulation results indicate the average SS of NCDU-TFET is 17.04mV/dec, which is much lower than that of DU-TFET. And the on-state current of NCDU-TFET is nearly three orders of magnitude higher than that of DU-TFET. So NCDU-TFET has the potential to be used as a low-power component for large-scale integrated circuits.

This article proposes an analytical model for channel potential and threshold voltage for negative capacitance junctionless FinFET (NC-JL FinFET). The Poisson's equation has been solved in collaboration with Landau–Khalatnikov equation to obtain analytical model for electrostatic potential distribution, threshold voltage and DIBL. The effect of fringing field on the potential distribution function due to source/drain spacer has also been taken into consideration. The results of proposed models are also validated and compared with simulated results of Sentaurus TCAD device simulator. The effect of various physical parameters like thickness of ferroelectric layer, fin thickness, spacer length, gate dielectric constant etc. on the performance of device has been studied. Further, the performance is also examined for different technology nodes and its (in context of) SCEs.

Capacitive multipliers have found wide applications in capacitive interfaces and other analog circuits requiring large value capacitors. Recently a new active building block (ABB) called second generation voltage conveyor (VCII) has been proved to be useful in many analog signal processing applications. Due to the interesting features offered by VCII, in this paper a new VCII based implementation of grounded capacitance multiplier is proposed employing two VCIIs, two resistors and one grounded capacitor. The circuit can produce both positive and negative multiplication factors in a range of −50 to +50. Its main features are wide frequency range, high resolution, low series resistance, simple structure, low power consumption and maximum percentage error of 7.8%. The circuit enjoys high frequency range up to 10 MHz, even if it employs a floating capacitor in its structure. The behavior of the proposed circuit is analysed by taking into account also the effects of VCII parasitic elements and non-ideal gains. SPICE simulation results using a 0.35 µm CMOS technology parameters are reported. The proposed circuit has been also experimentally tested by using AD844 as VCII. Measurement results on the standalone capacitance multiplier have shown a mean percentage error of 9% across the entire gain range. Finally, the application of the proposed circuit in realizing a low pass filter is also presented to demonstrate the proposed circuit feasibility.

Piezoelectric elements are widely used in structural vibration suppression. The applicable bipolar voltage of a piezoelectric element is unsymmetrical, but in most control systems, the voltage on the piezoelectric actuator is applied symmetrically, which greatly wastes the driving capability. In synchronized switching damping (SSD) approaches for structural vibration control, the damping effect depends on the effective voltage range on the piezoelectric actuator. A novel method of realizing unsymmetrical bipolar voltage with SSD method based on negative capacitance shunt circuit for vibration control is proposed for improvement of the control performance in this study. A resistance and a diode that added into constructed negative capacitance circuit are used to realize unsymmetrical bipolar voltage. The general expression of the switched voltage on the piezoelectric actuator is derived. The stability of negative capacitance shunt circuit is addressed. The added offset resistance in the negative capacitance circuit plays an important role in system stability. The simulation analysis results agree very well with the theoretical results, both of which reveal that the unsymmetrical voltage ratio depends on the resistance in the negative capacitance circuit. Finally, experiments are carried out to verify the designed circuit and the excellent damping performance.

A specialized heterojunction of p -ZnTe:N/CdTe:Mg/n-CdTe:I/GaAs for varicap and high response signal diode applications was epitaxially grown by using molecular beam epitaxy. Frequency dependence of the capacitance-voltage, conductance-voltage and series -resistance characteristics in the frequency spectrum from 10 kHz to 10 MHz at ambient temperature was investigated. An increase in the capacitance is observed especially at lower frequency range that can be attributed to the predominant effect of interface states. A negative capacitance is observed and is explained on the basis of the loss of interface charges or interface states localized between metal and semiconductor due to impact ionization process. The frequency and voltage dependencies of the series resistance were investigated and characteristic peaks were observed for the voltage dependence of series resistance under low-frequency range. Some important parameters such as barrier height, carrier concentration, cut off voltage were also estimated and discussed. The electrical characteristics of p -ZnTe:N/CdTe:Mg/n-CdTe:I/GaAs show a good candidacy for electronic and optoelectronic devices.

In this work, the negative capacitance phenomenon exhibited by ferroelectric materials has been incorporated in Junctionless Cylindrical Surrounding Gate (JLCSG) transistor and an analytical model has been developed to study the electrical characteristics of the device by taking into account Landau Khalatnikov equation along with parabolic potential approximation. Using the derived model various electrical parameters such as potential, gain, drain current, gate capacitance etc have been obtained. Silicon doped hafnium oxide has been incorporated as the ferroelectric material and exhaustive study has been done to study the impact of interfacial layer and metal workfunction on device characteristics as these have significant impact on the performance of Junctionless devices. It has been demonstrated by analytical model and TCAD simulations that by incorporating ferroelectric layer and optimizing metal work function and interfacial layer thickness, the device performance of JLCSG can be substantially improved.