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Since the challenges of maintaining the Moore's law - through traditional dimensional scaling or exploiting new materials properties - are becoming increasingly difficult, 3D integration technologies are gaining more and more attention and importance. At system level 3D-SOC solutions are of great interest, in particular those obtained through Wafer-to-Wafer (W2W) bonding due to superior overlay performance. In this paper we present the development of etch process modules for fine pitch via last interconnects realized on wafers with dielectric bonding and their integration in a packaging test chip, followed by electrical characterization.

Over the past few years, extreme wafer thinning has acquired more interest due to its importance in 3D stacked system architecture. This technique facilitates multi-wafer stacking for via last advanced packaging. From a cost and wafer integrity point of view, it has been demonstrated that the best process flow combines grinding with fast Si removal using Reactive Ion Etching (RIE). For this integration scheme, final thickness, and global flatness are key for subsequent steps. The wafer thinning performances are driven by several steps and can lead to lot, wafer to wafer and within wafer variations especially at the extreme edge. The first part of this study is to demonstrate stable wafer thinning with good control of the remaining Si (up to 5 μm) during the RIE process. This uses an innovative in-situ endpoint system (Near Infra-Red reflectometry) where the Si thickness is monitored whilst etching. The second part will focus on adjustment of the etch profile to compensate for incoming non-uniformity. This has been investigated from three different perspectives: Hardware modification where the ceramic ring surrounding the wafer is modified, process modification to change the etch front through changing the gas flow and plasma shape and changing the edge trim to introduce additional loading at the edge.