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Performance enhancement has always been a primary design goal for designers. Modern automation technology demands for reliable low cost controllers, required for specific applications. The restricted resources limits the number of functional units available on a processor which results into lowered performance. The better performance can be achieved with splitting existing functional unit into smaller independent units. The split of arithmetic and logic unit into two independent units namely arithmetic unit and logic unit, provides the facility for simultaneous operation by both of the units. This results into lesser execution time. The simulator Simplescalar has been modified to simulate split ALU. The benchmarks are run in order to collect performance statistics. The simulation parameters, including execution time have been recorded for standard simulator having integral ALU unit, and for split ALU unit and further compared to show enhanced performance with split ALU.

exponential increase in test cost is one of the new challenges being posed by technology scaling. This Paper has been aimed to deal with the issue of testing cost which adds to the chip cost. Here we propose a new pattern set for testing the arithmetic circuits which contains a minimum number of test vectors and easy to generate on the chip and hence supports at-speed testing of the circuit. Though maximum fault coverage is desired but practically generation of test vectors for testing of all the possible defects is not at all feasible. This leads to the modeling of defects as faults which facilitate for simplification of test generation process. Though various fault models have been proposed, the single stuck-at fault model is one of widely accepted model because of having closeness to the actual defects and also, it provide the algorithmic possibilities which, further helps in generation of test vectors. The desired smaller DPM (defective parts per million) levels for devices, creates the need for application of better fault models, which can model the defects in the most accurate fashion. This result in complex fault models which tends to make test generation tedious or even impossible and ultimately increase the test cost. Our motive is to cut down the test cost by finding the minimal number of test vectors for the test. If reduction in the patterns for one module is achieved, it would reduce the overall test cost. We propose universal pattern set which gives good fault coverage for arithmetic circuit with small set of vectors.

is a graphical record of the electrical tension of heart and has established as one the most important bio-signal used by cardiologists for diagnostic purposes and further to adopt an appropriate course of treatment. The difficulties faced in interpretation of ECG signals forced researchers to study about automatic detection of cardiac arrhythmia disorders. The data analysis techniques using specific computer software could easily interpret complex ECG signals, predict presence or absence of cardiac arrhythmia. This provides real time analysis and further facilitates for timely diagnosis. In this paper, Support Vector Machine (SVM) technique, using LibSVM3.1 has been applied to ECG dataset for arrhythmia classification in five categories. Out of these five categories, one is normal and four are arrhythmic beat categories. The dataset used in this study is 3003 arrhythmic beats out of which 2101 beats (70%) are used for training and remaining 902 beats (30%) have been used for testing purpose. Total performance accuracy is found to be around 95.21 % in this case.