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This paper proposes a procedure to analyze digital circuits in both Carbon Nanotube Field-Effect Transistors (CNTFET) and Complementary Metal-Oxide-Semiconductor (CMOS) technology for the purpose of comparison. The procedure is applied to study a NAND gate, with an emphasis on its applicability to analyze other digital circuits. To demonstrate this versatility, the procedure is also used to analyze a NOT gate in both CNTFET and CMOS technology. The paper presents the improvements achieved with CNTFET technology compared to CMOS. All simulations are conducted using the Advanced Design System (ADS) software, compatible with the Verilog-A programming language. Results from the analysis reveal that CNTFET technology exhibits superior performance, particularly at lower supply voltages. The paper also quantifies the differences in propagation delay, with CNTFET technology outperforming CMOS technology by a significant margin. [ABSTRACT FROM AUTHOR]

In this paper we present a procedure to study the effects of parasitic elements (capacitances, inductances and resistances) of interconnection lines in integrated circuits where Carbon Nanotubes are embedded. In particular the Drain/Source pads dimensions of CNT are analysed, as well as the interconnection lines between a CNT and an appropriate load are sized. In order to estimate parasitic elements in CNTs embedded integrated circuits, we analyse 50 nm technology. Moreover it is also possible for predictions analysis on 10 nm and 3 nm technology. We apply the proposed procedure to the design of a Common-Source amplifier, using a CNTFET model already proposed by us. The frequency domain simulations, obtained using the ADS simulator, show how the parasitic elements limit the performances of CNTs. In particular we obtain that the -3 dB cutting frequency of the examined amplifier full of parasitic elements increases as technology decreases. Moreover we repeat the proposed simulations using SPICE, obtaining results practically coincident but with the Verilog-A implementation we have mainly a simulation run time much shorter and a software much more concise and clear than schemes using ABM blocks in SPICE. [ABSTRACT FROM AUTHOR]

In this paper, the authors present a simulation study in order to carry out static and dynamic analysis of CNTFET-based digital circuits, in the semi-empirical compact model for CNTFETs, which was already proposed with, both the quantum capacitance effects and the sub-threshold currents. To verify the validity of the obtained results, they are compared with those of the Stanford-Source Virtual Carbon Nanotube Field-Effect Transistor (VS-CNFET) model. This comparison is made through some simulations of digital circuits. In particular they have considered XOR gate, but emphasizing that the proposed procedure can be applied to any logic gate based on CNTFET. As regards the static conditions, the two models behave in a manner virtually identical, while, as regards the dynamic analysis, there is a remarkable differences between two models in terms of propagation delays and rise and fall times. [ABSTRACT FROM AUTHOR]

In this paper, the authors present a comparison through a simulation study, among different hetero structure devices, like Metal Semiconductor Field Effect Transistor (MESFET), High Electron Mobility Transistor (HEMT), and Tunnel Field Effect Transistor (TFET), with reference to their applications in electronic field. In particular, MESFET and HEMT present good performance in power amplifiers and they are characterized by high mobility of the charge carriers that allows to consume less at high frequency. TFET is the newest experimental device, which has a very powerful application in logic circuits, ultra low-power specific analog ICs with better temperature strength and low-power SRAM. [ABSTRACT FROM AUTHOR]

The aim of this review paper is to define the role of SiGe HBTs within the Technology Revolution that will lead to a globally interconnected smart world. At first, the authors have presented the recent developments of SiGe BiCMOS technologies and their applications to unit circuit blocks and integrated solutions. Then modern HBT device structures, technological aspects, scaling strategies, design issues, and future directions are also discussed. TCAD-based simulations predict that SiGe HBTs with cut-off and maximum oscillation frequencies of 780 GHz and 2 THz, respectively will become feasible by the year 2030. [ABSTRACT FROM AUTHOR]

In this paper, the authors have illustrated a new kind of devices (molecular devices), able to work better at nanometer scale, with particular attention to molecular diodes. In particular, the I-V characteristics of a gated molecular diode were simulated, showing how an increase of the gate voltage involves an increase of the drain current. Then they proposed a simulation study which is obtained by SPICE simulator, in order to analyze and design some basic digital circuits (AND & OR) employing molecular diodes. In the light of obtained results, the molecular diodes are demonstrated as logic ports cannot be used because, although they follow input pulses, the logic levels in output and the noise margin obtained are not appropriate for electronic applications. [ABSTRACT FROM AUTHOR]

In this paper some of the possible applications in the biomedical field of the RFID technology are presented, giving an idea of the wide range of advantages that RFID devices are able to provide. In particular, those aspects of RFID technology were examined, which make possible the realization of miniaturized devices, implantable in the human body and powered from the outside, and can monitor the biological functions of individuals or even enable the therapy of diseases. Moreover, some aspects that need to be improved in the future research works are discussed such as the biocompatibility of the material for the implantable devices, the long-term exposure of the human body to electromagnetic fields, the interference caused by surrounding metallic parts, the attenuation of RF signals at particularly high frequency values and the implementation of a safe communication channel in order to guarantee the privacy of the individual. [ABSTRACT FROM AUTHOR]

This paper presents a light DC thermal model of recessed gate P-HEMT devices, based on the Chaibi model, where the authors have identified the transistor parameters having greater influence on the device behaviour for temperature variations. The main aims are to improve the accuracy of modelled I-V curves, in particular in the knee and saturation regions and above all to give the device source-drain current as a function of external voltages, as seen at the device gates, by-passing the very difficult measurement of parasitic resistances for the I-V characterisation. To verify the accuracy of the proposed model, the results are compared with those of Chaibi model, obtaining a negligible relative error, with however a compilation time and a run time much more low. [ABSTRACT FROM AUTHOR]